SCHA005B January   2015  – December 2022

PRODMIX  

  1.   Power-Up Behavior of Clocked Devices
  2. 1Unknown States at Power-Up
  3. 2Solutions to Unknown States at Power-Up
    1. 2.1 Use a Device with Clear or Preset Pins
    2. 2.2 Delay the Clock Edge with an RC Circuit and Schmitt Trigger Buffer
    3. 2.3 Wait Until VCC Has Ramped
  4. 3Trademarks
  5. 4Revision History

1 Power-Up Behavior of Clocked Devices

Some logic devices, such as flip-flops and shift registers, require the use of a clock input, typically designated CLK or CP. The state of the outputs of these devices change once an appropriate clock edge has occurred. Device datasheets specify whether the action occurs on a positive or negative edge of the clock. However, the behavior of a device upon power-up is not always specified before a valid clock edge has occurred.