SLASEB7D
June 2017 – December 2020
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Functional Block Diagrams
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagrams
7.2
Pin Attributes
7.3
Signal Descriptions
7.4
Pin Multiplexing
7.5
Buffer Type
7.6
Connection of Unused Pins
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Active Mode Supply Current Into VCC Excluding External Current
8.5
Typical Characteristics, Active Mode Supply Currents
8.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
8.7
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
8.8
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
8.9
Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
8.10
Typical Characteristics, Low-Power Mode Supply Currents
8.11
Typical Characteristics, Current Consumption per Module (1)
8.12
Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
8.13
Timing and Switching Characteristics
8.13.1
Power Supply Sequencing
8.13.1.1
Brownout and Device Reset Power Ramp Requirements
8.13.1.2
SVS
8.13.2
Reset Timing
8.13.2.1
Reset Input
8.13.3
Clock Specifications
8.13.3.1
Low-Frequency Crystal Oscillator, LFXT
8.13.3.2
High-Frequency Crystal Oscillator, HFXT
8.13.3.3
DCO
8.13.3.4
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
8.13.3.5
Module Oscillator (MODOSC)
8.13.4
Wake-up Characteristics
8.13.4.1
Wake-up Times From Low-Power Modes and Reset
8.13.4.2
Typical Wake-up Charges
8.13.4.3
Typical Characteristics, Average LPM Currents vs Wake-up Frequency
8.13.5
Digital I/Os
8.13.5.1
Digital Inputs
8.13.5.2
Digital Outputs
8.13.5.3
Typical Characteristics, Digital Outputs
8.13.6
LEA
8.13.6.1
Low-Energy Accelerator (LEA) Performance
8.13.7
Timer_A and Timer_B
8.13.7.1
Timer_A
8.13.7.2
Timer_B
8.13.8
eUSCI
8.13.8.1
eUSCI (UART Mode) Clock Frequency
8.13.8.2
eUSCI (UART Mode) Switching Characteristics
8.13.8.3
eUSCI (SPI Master Mode) Clock Frequency
8.13.8.4
eUSCI (SPI Master Mode) Switching Characteristics
8.13.8.5
eUSCI (SPI Master Mode) Timing Diagrams
8.13.8.6
eUSCI (SPI Slave Mode) Switching Characteristics
8.13.8.7
eUSCI (SPI Slave Mode) Timing Diagrams
8.13.8.8
eUSCI (I2C Mode) Switching Characteristics
8.13.8.9
eUSCI (SPI Slave Mode) Timing Diagrams
8.13.9
Segment LCD Controller
8.13.9.1
LCD_C Recommended Operating Conditions
8.13.9.2
LCD_C Electrical Characteristics
8.13.10
ADC12_B
8.13.10.1
12-Bit ADC, Power Supply and Input Range Conditions
8.13.10.2
12-Bit ADC, Timing Parameters
8.13.10.3
12-Bit ADC, Linearity Parameters
8.13.10.4
12-Bit ADC, Dynamic Performance With External Reference
8.13.10.5
12-Bit ADC, Dynamic Performance With Internal Reference
8.13.10.6
12-Bit ADC, Temperature Sensor and Built-In V1/2
8.13.10.7
12-Bit ADC, External Reference
8.13.10.8
Temperature Sensor Typical Characteristics
8.13.11
Reference
8.13.11.1
REF, Built-In Reference
8.13.12
Comparator
8.13.12.1
Comparator_E
8.13.13
FRAM
8.13.13.1
FRAM
8.13.14
USS
8.13.14.1
USS Recommended Operating Conditions
8.13.14.2
USS LDO
8.13.14.3
USSXTAL
8.13.14.4
USS HSPLL
8.13.14.5
USS SDHS
8.13.14.6
USS PHY Output Stage
8.13.14.7
USS PHY Input Stage, Multiplexer
8.13.14.8
USS PGA
8.13.14.9
USS Bias Voltage Generator
8.13.15
Emulation and Debug
8.13.15.1
JTAG and Spy-Bi-Wire Interface
9
Detailed Description
9.1
Overview
9.2
CPU
9.3
Ultrasonic Sensing Solution (USS) Module
9.4
Low-Energy Accelerator (LEA) for Signal Processing
9.5
Operating Modes
9.5.1
Peripherals in Low-Power Modes
9.5.2
Idle Currents of Peripherals in LPM3 and LPM4
9.6
Interrupt Vector Table and Signatures
9.7
Bootloader (BSL)
9.8
JTAG Operation
9.8.1
JTAG Standard Interface
9.8.2
Spy-Bi-Wire (SBW) Interface
9.9
FRAM Controller A (FRCTL_A)
9.10
RAM
9.11
Tiny RAM
9.12
Memory Protection Unit (MPU) Including IP Encapsulation
9.13
Peripherals
9.13.1
Digital I/O
9.13.2
Oscillator and Clock System (CS)
9.13.3
Power-Management Module (PMM)
9.13.4
Hardware Multiplier (MPY)
9.13.5
Real-Time Clock (RTC_C)
9.13.6
Measurement Test Interface (MTIF)
9.13.7
Watchdog Timer (WDT_A)
9.13.8
System Module (SYS)
9.13.9
DMA Controller
9.13.10
Enhanced Universal Serial Communication Interface (eUSCI)
9.13.11
TA0, TA1, and TA4
9.13.12
TA2 and TA3
9.13.13
TB0
9.13.14
ADC12_B
9.13.15
USS
9.13.16
Comparator_E
9.13.17
CRC16
9.13.18
CRC32
9.13.19
AES256 Accelerator
9.13.20
True Random Seed
9.13.21
Shared Reference (REF)
9.13.22
LCD_C
9.13.23
Embedded Emulation
9.13.23.1
Embedded Emulation Module (EEM) (S Version)
9.13.23.2
EnergyTrace++ Technology
9.14
Input/Output Diagrams
9.14.1
Port Function Select Registers (PySEL1 , PySEL0)
9.14.2
Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
9.14.3
Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
9.14.4
Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
9.14.5
Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
9.14.6
Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
9.14.7
Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
9.14.8
Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
9.14.9
Port P6 (P6.0) Input/Output With Schmitt Trigger
9.14.10
Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
9.14.11
Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
9.14.12
Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
9.14.13
Port P7 (P7.4) Input/Output With Schmitt Trigger
9.14.14
Port P7 (P7.5) Input/Output With Schmitt Trigger
9.14.15
Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
9.14.16
Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
9.14.17
Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
9.14.18
Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
9.14.19
Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
9.14.20
Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
9.14.21
Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
9.15
Device Descriptors (TLV)
9.16
Memory Map
9.16.1
Peripheral File Map
9.17
Identification
9.17.1
Revision Identification
9.17.2
Device Identification
9.17.3
JTAG Identification
10
Applications, Implementation, and Layout
10.1
Device Connection and Layout Fundamentals
10.1.1
Power Supply Decoupling and Bulk Capacitors
10.1.2
External Oscillator (HFXT and LFXT)
10.1.3
USS Oscillator (USSXT)
10.1.4
Transducer Connection to the USS Module
10.1.5
Charge Pump Control of Input Multiplexer
10.1.6
JTAG
10.1.7
Reset
10.1.8
Unused Pins
10.1.9
General Layout Recommendations
10.1.10
Do's and Don'ts
10.2
Peripheral- and Interface-Specific Design Information
10.2.1
ADC12_B Peripheral
10.2.1.1
Partial Schematic
10.2.1.2
Design Requirements
10.2.1.3
Detailed Design Procedure
10.2.1.4
Layout Guidelines
10.2.2
LCD_C Peripheral
10.2.2.1
Partial Schematic
10.2.2.2
Design Requirements
10.2.2.3
Detailed Design Procedure
10.2.2.4
Layout Guidelines
11
Device and Documentation Support
11.1
Getting Started
11.2
Device Nomenclature
11.3
Tools and Software
11.4
Documentation Support
11.5
Support Resources
11.6
Export Control Notice
11.7
Electrostatic Discharge Caution
11.8
Glossary
11.9
Trademarks
12
Mechanical, Packaging, and Orderable Information
1
Features
Best-in-class ultrasonic water-flow measurement with ultra-low power consumption
<25-ps differential time-of-flight (dTOF) accuracy
High-precision time measurement resolution of <5 ps
Ability to detect low flow rates (<1 liter per hour)
Approximately 3-µA overall current consumption with one measurement per second
Compliant to and exceeds ISO 4064, OIML R49, and EN 1434 accuracy standards
Ability to directly interface standard ultrasonic sensors (up to 2.5 MHz)
Integrated analog front end – ultrasonic sensing solution (USS)
Programmable pulse generation (PPG) to generate pulses at different frequencies
Integrated physical interface (PHY) with low-impedance (4-Ω) output driver to control input and output channels
High-performance high-speed 12-bit sigma-delta ADC (SDHS) with output data rates up to 8 Msps
Programmable gain amplifier (PGA) with –6.5 dB to 30.8 dB
High-performance phase-locked loop (PLL) with output range of 68 MHz to 80 MHz
Metering test interface (MTIF)
Pulse generator and pulse counter
Pulse rates up to 1016 pulses per second (p/s)
Count capacity up to 65535 (16 bits)
Operates in LPM3.5 with 200 nA (typical)
Low-energy accelerator (LEA)
Operation independent of CPU
4KB of RAM shared with CPU
Efficient 256-point complex FFT:
Up to 40× faster than
Arm®
Cortex®
-M0+ core
Embedded microcontroller
16-bit RISC architecture up to 16‑MHz clock
Wide supply voltage range from 3.6 V down to 1.8 V (minimum supply voltage is restricted by SVS levels, see the
SVS specifications
)
Optimized ultra-low-power modes
Active mode: approximately 120 µA/MHz
Standby mode with real-time clock (RTC) (LPM3.5): 450 nA
Shutdown (LPM4.5): 30 nA
Ferroelectric random access memory (FRAM)
Up to 256KB of nonvolatile memory
Ultra-low-power writes
Fast write at 125 ns per word (64KB in 4 ms)
Unified memory = program + data + storage in one space
10
15
write cycle endurance
Radiation resistant and nonmagnetic
Intelligent digital peripherals
32-bit hardware multiplier (MPY)
6-channel internal DMA
RTC with calendar and alarm functions
Six 16-bit timers with up to seven capture/compare registers each
32-bit and 16-bit cyclic redundancy check (CRC)
High-performance analog
16-channel analog comparator
12-bit SAR ADC featuring window comparator, internal reference, and sample-and-hold, up to 16 external input channels
Integrated LCD driver with contrast control for up to 264 segments
Multifunction input/output ports
Accessible bit-, byte-, and word-wise (in pairs)
Edge-selectable wake from LPM on all ports
Programmable pullup and pulldown on all ports
Code security
and encryption
128- or 256-bit AES security encryption and decryption coprocessor
Random number seed for random number generation algorithms
IP encapsulation protects memory from external access
FRAM provides inherent security advantages
Enhanced serial communication
Up to four eUSCI_A serial communication ports
UART with automatic baud-rate detection
IrDA encode and decode
Up to two eUSCI_B serial communication ports
I
2
C with multiple-slave addressing
Hardware UART or I
2
C bootloader (BSL)
Flexible clock system
Fixed-frequency DCO with 10 selectable factory-trimmed frequencies
Low-power low-frequency internal clock source (VLO)
32-kHz crystals (LFXT)
High-frequency crystals (HFXT)
Development tools and software (also see
Tools and Software
)
Ultrasonic Sensing Design Center graphical user interface
Ultrasonic sensing software library
EVM430-FR6047 water meter evaluation module
MSP-TS430PZ100E target socket board for 100-pin package
Free professional development environments with
EnergyTrace++ technology
MSP430Ware™
for
MSP430™
microcontrollers
Device Comparison
summarizes the available device variants and package options
SLASEB77493.
The RTC is clocked by a 3.7-pF crystal.