ZHCSBC5C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 7.12 I²C Control Port
    13. 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 7.15 Typical Performance Characteristics (Mono PBTL Mode)
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
        2. 9.5.2.2  Power Control Register (0x01)
        3. 9.5.2.3  Digital Control Register (0x02)
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
        7. 9.5.2.7  Analog Control Register (0x06)
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pullup Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Stereo BTL Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Mono PBTL Using Software Control
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Startup Procedures- Software Control Mode
          2. 10.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.3.2.3 Component Selection and Hardware Connections
            1. 10.2.3.2.3.1 I²C Pull-Up Resistors
            2. 10.2.3.2.3.2 Digital I/O Connectivity
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Mono PBTL Using Hardware Control
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.4.2.3 Component Selection and Hardware Connections
          4. 10.2.4.2.4 Digital I/O Connectivity
        3. 10.2.4.3 Application Curve
      5. 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Startup Procedures- Software Control Mode
          2. 10.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.5.2.3 Component Selection and Hardware Connections
            1. 10.2.5.2.3.1 I²C Pullup Resistors
            2. 10.2.5.2.3.2 Digital I/O Connectivity
          4. 10.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.5.3 Application Curve
      6. 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.6.2.3 Digital I/O Connectivity
        3. 10.2.6.3 Application Curve
      7. 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.7.1 Design Requirements
        2. 10.2.7.2 Detailed Design Procedure
          1. 10.2.7.2.1 Startup Procedures- Software Control Mode
          2. 10.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.7.2.3 Component Selection and Hardware Connections
            1. 10.2.7.2.3.1 I²C Pull-Up Resistors
            2. 10.2.7.2.3.2 Digital I/O Connectivity
        3. 10.2.7.3 Application Curve
      8. 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.8.2.3 Component Selection and Hardware Connections
          4. 10.2.8.2.4 Digital I/O Connectivity
        3. 10.2.8.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

1 特性

  • 音频 I/O 配置：
    • 单路立体声 I²S 输入
    • 立体声桥接负载 (BTL) 或单声道并行桥接负载 (PBTL) 运行
    • 32kHz、44.1kHz、48kHz、88.2kHz、96kHz 采样速率
  • 常规运行 特性：
    • 可选硬件或软件控制
    • 集成数字输出削波器
    • 可编程 I²C 地址（1101100[R/W]或1101101[R/W]）
    • 闭环放大器架构
    • 可调节扬声器放大器开关频率
  • 稳定性 特性：
    • 时钟误差、直流和短路保护
    • 过热保护和可编程过流保护
  • 音频性能（PVDD = 12V，RSPK = 8Ω，SPK_GAIN[1:0] 引脚 = 01）”
    • 闲置通道噪声 = 65µVrms（输入信噪比）
    • THD+N = 0.09%（功率为 1W，频率为 1kHz）
    • SNR = 100dB A-Wtd（以THD+N = 1% 为基准）

2 应用

  • LCD/LED TV 和多用途监视器
  • 条形音箱，扩展坞，PC 音频
  • 通用音频设备

3 说明

TAS5760L是一款立体声 I2S 输入器件，具有硬件和软件 (I²C) 控制模式、集成数字削波器、多种增益选项并且电源运行电压范围较大，支持其适用于多种 应用非常有用。TAS5760L运行电压范围为 4.5V 至15VDC 的标称电源电压。

输出金属氧化物半导体场效应晶体管 (MOSFET) 的 120mΩ DS(ON) 兼顾散热性能与器件成本，二者相得益彰。此外，该器件采用耐热增强型 48-Pin TSSOP封装，在现代消费类电子器件的较高工作环境温度下展现出优异的性能。

整个 TAS5760xx 系列均采用 48-Pin TSSOP封装，并且所有系列成员器件之间彼此引脚到引脚兼容。另外，对于可能不需要耳机/线路驱动器且 不要求引脚至引脚兼容， 但希望解决方案实现最小化的应用，TAS5760M 和 TAS5760L 器件可采用 32 引脚薄型小外形尺寸 (TSSOP) 封装。TAS5760xx 系列所有器件的 I2C 寄存器映射是相同的，这样一来，当需要根据系统级要求更换器件时，可以减少二次开发的工作量。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TAS5760L HTSSOP (48) 12.50mm x 6.10mm
HTSSOP (32) 11mm × 6.2mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

功能方框图

TAS5760L BD_TAS5760x.gif

输出功率与 PVDD 间的关系

TAS5760L G001_BTL_384_POvsVDD_SLOS781.png

NOTE:

热限值由 TAS5760xxEVM 确定