ZHCSID6A
December 2018 – December 2018
LMK05318
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
简化方框图
4
修订历史记录
5
(说明 (续))
6
Pin Configuration and Functions
Pin Functions
6.1
Device Start-Up Modes
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information: 4-Layer JEDEC Standard PCB
7.5
Thermal Information: 10-Layer Custom PCB
7.6
Electrical Characteristics
7.7
Timing Diagrams
7.8
Typical Characteristics
8
Parameter Measurement Information
8.1
Output Clock Test Configurations
9
Detailed Description
9.1
Overview
9.1.1
ITU-T G.8262 (SyncE) Standards Compliance
9.2
Functional Block Diagram
9.2.1
PLL Architecture Overview
9.2.2
DPLL Mode
9.2.3
APLL-Only Mode
9.3
Feature Description
9.3.1
Oscillator Input (XO_P/N)
9.3.2
Reference Inputs (PRIREF_P/N and SECREF_P/N)
9.3.3
Clock Input Interfacing and Termination
9.3.4
Reference Input Mux Selection
9.3.4.1
Automatic Input Selection
9.3.4.2
Manual Input Selection
9.3.5
Hitless Switching
9.3.5.1
Hitless Switching With 1-PPS Inputs
9.3.6
Gapped Clock Support on Reference Inputs
9.3.7
Input Clock and PLL Monitoring, Status, and Interrupts
9.3.7.1
XO Input Monitoring
9.3.7.2
Reference Input Monitoring
9.3.7.2.1
Reference Validation Timer
9.3.7.2.2
Amplitude Monitor
9.3.7.2.3
Frequency Monitoring
9.3.7.2.4
Missing Pulse Monitor (Late Detect)
9.3.7.2.5
Runt Pulse Monitor (Early Detect)
9.3.7.2.6
Phase Valid Monitor for 1-PPS Inputs
9.3.7.3
PLL Lock Detectors
9.3.7.4
Tuning Word History
9.3.7.5
Status Outputs
9.3.7.6
Interrupt
9.3.8
PLL Relationships
9.3.8.1
PLL Frequency Relationships
9.3.8.2
Analog PLLs (APLL1, APLL2)
9.3.8.3
APLL Reference Paths
9.3.8.3.1
APLL XO Doubler
9.3.8.3.2
APLL1 XO Reference (R) Divider
9.3.8.3.3
APLL2 Reference (R) Dividers
9.3.8.4
APLL Phase Frequency Detector (PFD) and Charge Pump
9.3.8.5
APLL Feedback Divider Paths
9.3.8.5.1
APLL1 N Divider With SDM
9.3.8.5.2
APLL2 N Divider With SDM
9.3.8.6
APLL Loop Filters (LF1, LF2)
9.3.8.7
APLL Voltage Controlled Oscillators (VCO1, VCO2)
9.3.8.7.1
VCO Calibration
9.3.8.8
APLL VCO Clock Distribution Paths (P1, P2)
9.3.8.9
DPLL Reference (R) Divider Paths
9.3.8.10
DPLL Time-to-Digital Converter (TDC)
9.3.8.11
DPLL Loop Filter (DLF)
9.3.8.12
DPLL Feedback (FB) Divider Path
9.3.9
Output Clock Distribution
9.3.10
Output Channel Muxes
9.3.11
Output Dividers (OD)
9.3.12
Clock Outputs (OUTx_P/N)
9.3.12.1
AC-Differential Output (AC-DIFF)
9.3.12.2
HCSL Output
9.3.12.3
1.8-V LVCMOS Output
9.3.12.4
Output Auto-Mute During LOL
9.3.13
Glitchless Output Clock Start-Up
9.3.14
Clock Output Interfacing and Termination
9.3.15
Output Synchronization (SYNC)
9.3.16
Zero-Delay Mode (ZDM) Synchronization for 1-PPS Input and Output
9.4
Device Functional Modes
9.4.1
Device Start-Up Modes
9.4.1.1
EEPROM Mode
9.4.1.2
ROM Mode
9.4.2
PLL Operating Modes
9.4.2.1
Free-Run Mode
9.4.2.2
Lock Acquisition
9.4.2.3
Locked Mode
9.4.2.4
Holdover Mode
9.4.3
PLL Start-Up Sequence
9.4.4
Digitally-Controlled Oscillator (DCO) Mode
9.4.4.1
DCO Frequency Step Size
9.4.4.2
DCO Direct-Write Mode
9.4.5
Zero-Delay Mode Synchronization
9.5
Programming
9.5.1
Interface and Control
9.5.2
I2C Serial Interface
9.5.2.1
I2C Block Register Transfers
9.5.3
SPI Serial Interface
9.5.3.1
SPI Block Register Transfer
9.5.4
Register Map and EEPROM Map Generation
9.5.5
General Register Programming Sequence
9.5.6
EEPROM Programming Flow
9.5.6.1
EEPROM Programming Using Method #1 (Register Commit)
9.5.6.1.1
Write SRAM Using Register Commit
9.5.6.1.2
Program EEPROM
9.5.6.2
EEPROM Programming Using Method #2 (Direct Writes)
9.5.6.2.1
Write SRAM Using Direct Writes
9.5.6.2.2
User-Programmable Fields In EEPROM
9.5.7
Read SRAM
9.5.8
Read EEPROM
9.5.9
EEPROM Start-Up Mode Default Configuration
10
Application and Implementation
10.1
Application Information
10.1.1
Device Start-Up Sequence
10.1.2
Power Down (PDN) Pin
10.1.3
Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
10.1.3.1
Mixing Supplies
10.1.3.2
Power-On Reset (POR) Circuit
10.1.3.3
Powering Up From a Single-Supply Rail
10.1.3.4
Power Up From Split-Supply Rails
10.1.3.5
Non-Monotonic or Slow Power-Up Supply Ramp
10.1.4
Slow or Delayed XO Start-Up
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
10.3
Do's and Don'ts
11
Power Supply Recommendations
11.1
Power Supply Bypassing
11.2
Device Current and Power Consumption
11.2.1
Current Consumption Calculations
11.2.2
Power Consumption Calculations
11.2.3
Example
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.3
Thermal Reliability
12.3.1
Support for PCB Temperature up to 105°C
13
器件和文档支持
13.1
器件支持
13.1.1
TICS Pro
13.1.2
相关文档
13.2
接收文档更新通知
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
术语表
14
机械、封装和可订购信息
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
RGZ|48
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsid6a_oa
zhcsid6a_pm
1
特性
一个数字锁相环 (DPLL),具有:
无中断切换:±50ps 相位瞬态
具有快速锁定功能的可编程环路带宽
使用低成本 TCXO/OCXO 实现符合标准的同步和保持模式
两个具备业界领先性能的模拟锁相环 (APLL):
312.5MHz 频率下 50fs RMS 抖动 (APLL1)
155.52MHz 频率下 125fs RMS 抖动 (APLL2)
两个基准时钟输入
基于优先级的输入选择
在缺失参考时实现数字保持
具有可编程驱动器的八个时钟输出
多达 6 个不同的输出频率
AC-LVDS、AC-CML、AC-LVPECL、HCSL 和 1.8V LVCMOS 输出格式
加电后自定义时钟的 EEPROM/ROM
灵活的配置选项
输入和输出为 1Hz (1PPS) 至 800MHz
XO/TCXO/OCXO 输入:10 至 100MHz
DCO 模式:< 0.001ppb/阶跃,可进行精确的时钟控制(IEEE 1588 PTP 从运行)
先进的时钟监控和状态
I
2
C 或 SPI 接口
PSNR:–83dBc(3.3V 电源下噪声为 50mVpp)
3.3V 电源,提供 1.8V、2.5V 或 3.3V 输出
工业温度范围:-40°C 至 +85°C