SCLS116H December 1982 – December 2015 SN54HC165 , SN74HC165
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74HC165D | SOIC (16) | 10.00 mm × 6.20 mm |
SN74HC165DB | SSOP (16) | 8.20 mm × 6.50 mm |
SN74HC165N | PDIP (16) | 6.60 mm × 18.92 mm |
SN74HC165NS | SO (16) | 8.20 mm × 9.90 mm |
SN74HC165PW | TSSOP (16) | 6.60 mm × 5.10 mm |
SN54HC165FK | LCCC (20) | 9.09 mm × 9.09 mm |
SN54HC165J | CDIP (16) | 21.34 mm × 7.52 mm |
SN54HC165W | CFP (16) | 9.40 mm × 7.75 mm |