SLAS513C February   2007  – December 2014 TLV320AIC3105

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Related Devices
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Control Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Fully Differential Line Output Drivers
      6. 10.3.6  Analog High-Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  MICBIAS Generation
      9. 10.3.9  Short-Circuit Output Protection
      10. 10.3.10 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Capless Headphone and External Speaker Amp
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 AC-Coupled Headphone Out With Separate Line Outputs and External Speaker Amplifier
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

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1 Features

  • Stereo Audio DAC
    • 102-dBA Signal-to-Noise Ratio
    • 16/20/24/32-Bit Data
    • Supports Rates From 8 kHz to 96 kHz
    • 3D/Bass/Treble/EQ/De-Emphasis Effects
    • Flexible Power Saving Modes and Performance are Available
  • Stereo Audio ADC
    • 92-dBA Signal-to-Noise Ratio
    • Supports Rates From 8 kHz to 96 kHz
    • Digital Signal Processing and Noise Filtering Available During Record
  • Six Audio Input Pins
    • Six Stereo Single-Ended Inputs
  • Six Audio Output Drivers
    • Stereo Fully Differential or Single-Ended Headphone Drivers
    • Fully Differential Stereo Line Outputs
  • Low Power: 14-mW Stereo 48-kHz Playback With 3.3-V Analog Supply
  • Ultralow-Power Mode with Passive Analog Bypass
  • Programmable Input/Output Analog Gains
  • Automatic Gain Control (AGC) for Record
  • Programmable Microphone Bias Level
  • Programmable PLL for Flexible Clock Generation
  • I2C Control Bus
  • Audio Serial Data Bus Supports I2S, Left/Right-Justified, DSP, and TDM Modes
  • Extensive Modular Power Control
  • Power Supplies:
    • Analog: 2.7 V–3.6 V.
    • Digital Core: 1.525 V–1.95 V
    • Digital I/O: 1.1 V–3.6 V
  • Package: 5-mm × 5-mm 32-Pin VQFN

2 Applications

  • Digital Cameras
  • Smart Cellular Phones

3 Description

The TLV320AIC3105 is a low-power stereo audio codec with multiple single-ended inputs and a stereo headphone amplifier. The output stages are programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

The record path of the TLV320AIC3105 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during optical zooming in digital cameras. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLV320AIC3105 VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Diagram

AIC3105_SimplifiedDiagram.png