TPD4S012 4-Channel ESD Solution for USB-HS/USB OTG/USB Charger Interface
- SLVS928B March 2009 – August 2014 TPD4S012
  
  UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

Full reading width

DATA SHEET

TPD4S012 4-Channel ESD Solution for USB-HS/USB OTG/USB Charger Interface

1 Features

Integrated ESD Clamps on all Pins
USB Signal Pins (D+, D–, ID)
- 0.8-pF Line Capacitance
Supports Data Rates in Excess of 480 Mbps
IEC 61000-4-2 ESD Protection (Level 4 Contact)
- ±10-kV IEC 61000-4-2 Contact Discharge
IEC 61000-4-5 Surge
- 3 Amps Peak Pulse Current

2 Applications

Cellular Phones
Digital Cameras
Global Positioning Systems (GPS)
Portable Digital Assistants (PDA)
Portable Computers

3 Description

The TPD4S012 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array for USB chargers and USB On-The-Go (OTG) interfaces.

The TPD4S012 provides IEC 61000-4-2 system level ESD Protection featuring 15 V tolerance on the V_BUS line. The device is ideal for providing circuit protection for USB charger and OTG applications due to its high-voltage tolerance at the V_BUS line and small flow-through package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPD4S012	SON (6)	1.45 mm x 1.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Typical Application Schematic

4 Revision History

Changes from A Revision (November 2009) to B Revision

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configurations and Functions

N.C. – Not internally connected

D+, D–, and ID pins are exact equivalent ESD clamp circuits. Any of these pins can be connected to any other D+, D–, or ID pin if it becomes easier to route the traces from the USB connector.

Pin Functions

PIN		TYPE	DESCRIPTION
DRY PIN NO.	NAME	TYPE	DESCRIPTION
1	D+	ESD clamp	Provides ESD protection to the high-speed differential data lines
2	D–	ESD clamp	Provides ESD protection to the high-speed differential data lines
3	ID	ESD clamp	Provides ESD protection to the high-speed differential data lines
4	GND	PWR	Ground
5	N.C.	–	Not internally connected
6	V_BUS	ESD clamp	ESD clamp for high-voltage tolerant V_BUS line(s)

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

PARAMETER			MIN	MAX	UNIT
	V_BUS voltage tolerance	V_BUS pin	–0.3	20	V
	IO voltage tolerance	D+, D–, ID pins	–0.3	6	V
T_A	Operating free-air temperature range		–40	85	°C
	IEC 61000-4-2 Contact Discharge	D+, D–, ID		±10	kV
	IEC 61000-4-2 Contact Discharge	V_BUS pin		±10	kV
	IEC 61000-4-2 Air-Gap Discharge	D+, D–, ID		±10	kV
	IEC 61000-4-2 Air-Gap Discharge	V_BUS pin		±9	kV
	IEC 61000-4-5 Surge (t_p = 8/20 μs)	Peak pulse Power (All pins)		60	W
	IEC 61000-4-5 Surge (t_p = 8/20 μs)	Peak pulse current (All Pins)		3	A

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	125	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2.5	2.5	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–1	1	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
T_A Operating free-air Temperature Range		–40	85	°C
Operating Voltage	V_BUS Pin	0	15	V
Operating Voltage	D+, D–, ID Pins	0	5.5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD4S012	UNIT
		DRY
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	461.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	219.6
R_θJB	Junction-to-board thermal resistance	343.7
ψ_JT	Junction-to-top characterization parameter	162.5
ψ_JB	Junction-to-board characterization parameter	343.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_VBUS	V_BUS operating current	V_BUS = 19 V	D+, D–, ID pins open		0.1	0.5	μA
I_IO	IO port current	V_IO= 2.5 V, V_BUS = 5 V	D+, D–, ID pins		0.1	0.5	μA
V_D	Diode forward voltage	I_IO = 8 mA	D+, D–, ID pins (lower clamp diode)	0.6	0.8	0.95	V
C_VBUS	V_BUS pin capacitance	V_BUS = 5 V			11	15	pF
C_IO	IO capacitance	V_IO = 2.5 V	D+, D–, ID pins		0.8	1	pF
R_DYN	Dynamic resistance	I_IO = 1.5 A	D+, D–, ID, and V_BUS pins, including central clamp dioded during positive ESD pulse		1.2		Ω
R_DYN	Dynamic resistance	I_IO = 1 A	D+, D–, ID, and V_BUS pins, including central clamp diode during negative ESD pulse		1		Ω
V_BR	Breakdown voltage	I_IO = 1 mA	D+, D–, ID pins	6	9		V
V_BR	Breakdown voltage	I_IO = 1 mA	V_BUS pin(s)	20	24		V

6.6 Typical Characteristics

Figure 1. Peak Pulse Power Waveform at the D+, D–, or ID Pin

Figure 3. D+, D–, or ID Clamp Voltage Under ESD Event

Figure 5. D+, D–, or ID Capacitance, T_A = 27°C

Figure 7. IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div

Figure 9. V_BUS IEC Clamping Waveform, 8 kV Contact, 25 ns/div

Figure 2. Peak Pulse Power Waveform at the V_BUS Pin

Figure 4. V_BUS Clamp Voltage Under ESD Event

Figure 6. V_BUS Capacitance, T_A = 27°C

Figure 8. IEC Clamping Waveform, –8 kV Contact, D+, 25 ns/div

Figure 10. V_BUS IEC Clamping Waveform, –8 kV Contact, 25 ns/div

7 Detailed Description

7.1 Overview

The TPD4S012 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array for USB chargers and USB On-The-Go (OTG) interfaces.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Integrated ESD Clamps

Integrated ESD Clamps on the D+, D–, V_BUS, and ID pins provide single-chip ESD protection for USB High Speed, USB-OTG, and USB charger interfaces.

7.3.2 USB Signal Pins

D+, D– and ID USB Signal pins have low capacitance (0.8 pF Typ).

7.3.3 V_BUS Line

The V_BUS line has a 11 pF (Typ) capacitance.

7.3.4 Supports Data Rates in Excess of 480 Mbps

The low capacitance (0.8 pF Typ) of the data lines supports speeds in excess of 480 Mbps.

7.3.5 IEC 61000-4-2 (Level 4 Contact)

IEC 61000-4-2 (Level 4 contact) system level ESD compliance measured at the D+, D– and ID pins is rated for ±10 kV contact and air-gap discharge.

7.3.6 IEC 61000-4-5 Surge

IEC 61000-4-5 system level surge compliance measured at D+, D–, ID, and V_BUS pins rated to 3 A of peak pulse current.

7.4 Device Functional Modes

The TPD4S012 is a passive integrated circuit that triggers when voltages are above V_BR or below the lower diode's V_f. During ESD events, voltages as high as ±10 kV (contact) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4S012 (usually within 10's of nano-seconds), the device reverts to passive.

8 Applications and Implementation

8.1 Application Information

The TPD4S012 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array for USB chargers and USB On-The-Go (OTG) interfaces.

8.2 Typical Application

If the ID pin is not used, it can be left floating.

Figure 11. Typical Application Schematic

8.2.1 Design Requirements

For this design example, a single TPD4S012 is used to protect all pins of a micro/mini USB connector.

Given the USB application, the following parameters are known.

DESIGN PARAMETER	VALUE
Signal range on D+, D–, and ID	0 V to 5 V
Signal range on V_BUS	0 V to 5 V
Operating Frequency	240 MHz

8.2.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon; the designer needs to know the following:

Signal range on all the protected lines
Operating frequency

8.2.2.1 Signal Range on D+, D-, ID and V_BUS pins

The TPD4S012 has 3 pins which support 0 to 5.5 V signals, these are suited for the D+, D–, and ID pins. The V_BUS pin is suitable for the VBUS line, and has the benefit of being tolerant of voltages up to 16 V

8.2.2.2 Operating Frequency

The 0.8 pF (Typ) of the TPD4S012 support data rates in excess of 480 Mbps.

8.2.3 Application Curve

Figure 12. IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div

Figure 14. V_BUS IEC Clamping Waveform, 8 kV Contact, 25 ns/div

Figure 13. IEC Clamping Waveform, –8 kV Contact, D+, 25 ns/div

Figure 15. V_BUS IEC Clamping Waveform, –8 kV Contact, 25 ns/div

9 Power Supply Recommendations

This family of devices are passive ESD protection devices and there is no need to power them. Care should be taken to not violate the maximum voltage specification to ensure that the device functions properly. The V_BUS TVS diode can tolerate up to a 15 V signal. The D+, D–, and ID pins tolerate up to a 5.5 V signal.

10 Layout

10.1 Layout Guidelines

The optimum placement is as close to the connector as possible.
- EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
- The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
- Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

This application is typical of a mobile USB platform with an ID pin in addition to the D+, D–, and V_BUS pins.

Figure 16. Using DRY Package

11 Device and Documentation Support

11.1 Trademarks

All other trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.