CSD22205L –8-V P-Channel NexFET™ Power MOSFET

1 Features

Low resistance
Small footprint 1.2 mm × 1.2 mm
Low profile 0.36-mm height
Lead free
Gate-source voltage clamp
Gate ESD protection
RoHS compliant
Halogen free

2 Applications

Battery management
Load switch
Battery protection

3 Description

This –8-V, 8.2-mΩ, 1.2-mm × 1.2-mm Land Grid Array (LGA) NexFET™ device has been designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. The Land Grid Array (LGA) package is a silicon chip scale package with metal pads instead of solder balls.

R_DS(on) vs V_GS

Product Summary

T_A = 25°C		VALUE		UNIT
V_DS	Drain-to-Source Voltage	–8		V
Q_g	Gate Charge Total (–4.5 V)	6.5		nC
Q_gd	Gate Charge Gate-to-Drain	1.0		nC
R_DS(on)	Drain-to-Source On-Resistance	V_GS = –1.5 V	30	mΩ
		V_GS = –1.8 V	20
		V_GS = –2.5 V	11.5
		V_GS = –4.5 V	8.2
V_GS(th)	Threshold Voltage	–0.7		V

Device Information⁽¹⁾

DEVICE	QTY	MEDIA	PACKAGE	SHIP
CSD22205L	3000	7-Inch Reel	1.20-mm × 1.20-mm Land Grid Array Package	Tape and Reel
CSD22205LT	250	7-Inch Reel	1.20-mm × 1.20-mm Land Grid Array Package	Tape and Reel

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C		VALUE	UNIT
V_DS	Drain-to-Source Voltage	–8	V
V_GS	Gate-to-Source Voltage	–6	V
I_D	Continuous Drain Current⁽¹⁾	–7.4	A
I_DM	Pulsed Drain Current⁽²⁾	–71	A
P_D	Power Dissipation⁽¹⁾	0.6	W
T_J, T_stg	Operating Junction Temperature, Storage Temperature	–55 to 150	°C

(1) Min Cu R_θJA = 225°C/W.

(2) Pulse width ≤ 100 μs, duty cycle ≤ 1%.

Figure 3-1 Top View and Circuit Configuration

4 Revision History

Changes from Revision A (August 2017) to Revision B (February 2022)

Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height.Go
Changed CSD22205L Package Dimensions image height from 0.35 mm to 0.36 mm.Go

Changes from Revision * (May 2017) to Revision A (August 2017)

Changed the units for timing parameters from µs : to ns (nanoseconds) in the Section 5.1 tableGo

5 Specifications

5.1 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage	V_GS = 0 V, I_D = –250 μA	–8			V
I_DSS	Drain-to-source leakage current	V_GS = 0 V, V_DS = –6.4 V			–100	nA
I_GSS	Gate-to-source leakage current	V_DS = 0 V, V_GS = –6 V			–100	nA
V_GS(th)	Gate-to-source threshold voltage	V_DS = V_GS, I_D = –250 μA	–0.4	–0.7	–1.05	V
R_DS(on)	Drain-to-source on-resistance	V_GS = –1.5 V, I_D = –0.2 A		30		mΩ
		V_GS = –1.8 V, I_D = –1 A		20	40
		V_GS = –2.5 V, I_D = –1 A		11.5	15.0
		V_GS = –4.5 V, I_D = –1 A		8.2	9.9
g_fs	Transconductance	V_DS = –0.8 V, I_D = –1 A		10.4		S
DYNAMIC CHARACTERISTICS
C_ISS	Input capacitance	V_GS = 0 V, V_DS = –4 V, ƒ = 1 MHz		1070	1390	pF
C_OSS	Output capacitance			560	730	pF
C_RSS	Reverse transfer capacitance			190	250	pF
R_G	Series gate resistance			30		Ω
Q_g	Gate charge total (–4.5 V)	V_DS = –4 V, I_D = –1 A		6.5	8.5	nC
Q_gd	Gate charge gate-to-drain			1.0		nC
Q_gs	Gate charge gate-to-source			1.2		nC
Q_g(th)	Gate charge at V_th			0.7		nC
Q_OSS	Output charge	V_DS = –4 V, V_GS = 0 V		4.1		nC
t_d(on)	Turnon delay time	V_DS = –4 V, V_GS = –4.5 V, I_D = –1 A , R_G = 0 Ω		30		ns
t_r	Rise time			14		ns
t_d(off)	Turnoff delay time			70		ns
t_f	Fall time			32		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage	I_S = –1 A, V_GS = 0 V		–0.68	–1.0	V
Q_rr	Reverse recovery charge	V_DS= –4 V, I_F = –1 A, di/dt = 200 A/μs		16		nC
t_rr	Reverse recovery time	V_DS= –4 V, I_F = –1 A, di/dt = 200 A/μs		38		ns