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  • CSD87588N Synchronous Buck NexFET Power Block II

    • SLPS384D March   2013  – April 2015 CSD87588N

      PRODUCTION DATA.  

  • CONTENTS
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  • CSD87588N Synchronous Buck NexFET Power Block II
  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. 6.1.4.1 Design Example
        2. 6.1.4.2 Calculating Power Loss
        3. 6.1.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87588N Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87588N Embossed Carrier Tape Dimensions
  10. IMPORTANT NOTICE

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DATA SHEET

CSD87588N Synchronous Buck NexFET Power Block II

1 Features

  • Half-Bridge Power Block
  • 90% System Efficiency at 20 A
  • Up to 25 A Operation
  • High Density – 5 mm x 2.5 mm LGA Footprint
  • Double Side Cooling Capability
  • Ultra-Low Profile – 0.48 mm Max
  • Optimized for 5 V Gate Drive
  • Low Switching Losses
  • Low Inductance Package
  • RoHS Compliant
  • Halogen Free
  • Pb Free

2 Applications

  • Synchronous Buck Converters
    • High-Current, Low Duty Cycle Applications
  • Multiphase Synchronous Buck Converters
  • POL DC-DC Converters

3 Description

The CSD87588N NexFET™ power block II is a highly-optimized design for synchronous buck applications offering high current and high efficiency capability in a small 5 mm × 2.5 mm outline. Optimized for 5 V gate drive applications, this product offers an efficient and flexible solution capable of providing a high density power supply when paired with any 5 V gate driver from an external controller/driver.


Ordering Information(1)

Device Media Qty Package Ship
CSD87588N 13-Inch Reel 2500 5 x 2.5 LGA Tape and Reel
CSD87588NT 7-Inch Reel 250
  1. For all available packages, see the orderable addendum at the end of the data sheet.


CSD87588N Pin_Out.gif

Typical Circuit

CSD87588N Front_Page_Img_3.gif

Typical Power Block Efficiency and Power Loss

CSD87588N front_page_SLPS384_F.png

4 Revision History

Changes from C Revision (June 2014) to D Revision

  • Changed capacitance units to read pF in Figure 15Go
  • Changed capacitance units to read pF in Figure 16Go

Changes from B Revision (January 2014) to C Revision

  • Changed "Pb-Free Terminal Plating" feature to state "Pb Free" Go

Changes from A Revision (May 2013) to B Revision

  • Added small reel infoGo
  • Updated Figure 5Go
  • Updated Figure 6Go
  • Updated Figure 7Go
  • Updated Figure 8Go
  • Changed figure reference to Figure 29 in electrical performanceGo

Changes from * Revision (March 2013) to A Revision

  • Changed RθJC-PCBTo: RθJC in the Thermal Information tableGo

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to VSW –20 20
BG to PGND –20 20
IDM Pulsed Current Rating(2) 50 A
PD Power Dissipation(3) 6 W
EAS Avalanche Energy Sync FET, ID = 45, L = 0.1 mH 101 mJ
Control FET, ID = 26, L = 0.1 mH 34
TJ Operating Junction –55 150 °C
Tstg Storage Temperature Range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse Duration ≤50 µs, duty cycle ≤0.01
(3) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VGS Gate Drive Voltage 4.5 16 V
VIN Input Supply Voltage 24 V
ƒSW Switching Frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating Current No Airflow 25 A
With Airflow (200 LFM) 30 A
With Airflow + Heat Sink 35 A
TJ Operating Temperature 125 °C

5.3 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (Min Cu) (1) 170 °C/W
Junction-to-ambient thermal resistance (Max Cu) (2)(1) 70
RθJC Junction-to-case thermal resistance (Top of package) (1) 3.7
Junction-to-case thermal resistance (PGND Pin) (1) 1.25
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.

5.4 Power Block Performance

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power Loss(1) VIN = 12 V, VGS = 5 V
VOUT = 1.3 V, IOUT = 15 A
ƒSW = 500 kHz
LOUT = 0.29 µH, TJ = 25ºC 		2.1 W
IQVIN VIN Quiescent Current TG to TGR = 0 V
BG to PGND = 0 V 		10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 FET Q2 FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 100 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.1 1.9 1.1 1.9 V
RDS(on) Drain-to-Source On Resistance VGS = 4.5 V, IDS = 15 A 10.4 12.5 3.5 4.2 mΩ
VGS = 10 V, IDS = 15 A 8 9.6 2.9 3.5
gƒs Transconductance VDS = 10 V, IDS = 15 A 43 93 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance (1) VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 566 736 2310 3000 pF
COSS Output Capacitance (1) 341 444 682 887 pF
CRSS Reverse Transfer Capacitance (1) 10.3 13.4 62 80.4 pF
RG Series Gate Resistance (1) 1.2 2.4 1.1 2.2 Ω
Qg Gate Charge Total (4.5 V) (1) VDS = 15 V,
IDS = 15 A		 3.2 4.1 13.7 17.9 nC
Qgd Gate Charge - Gate-to-Drain 0.7 4.3 nC
Qgs Gate Charge - Gate-to-Source 1.4 4.3 nC
Qg(th) Gate Charge at Vth 0.8 2.8 nC
QOSS Output Charge VDD = 12 V, VGS = 0 V 7 18.6 nC
td(on) Turn On Delay Time VDS = 15 V, VGS = 4.5 V,
IDS = 15 A, RG = 2 Ω		 7.3 12.1 ns
tr Rise Time 31.6 36.7 ns
td(off) Turn Off Delay Time 10.2 20.1 ns
tƒ Fall Time 5.0 6.3 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 15 A, VGS = 0 V 0.85 0.78 V
Qrr Reverse Recovery Charge Vdd = 15 V, IF = 15 A,
di/dt = 300 A/μs		 12.5 26.7 nC
trr Reverse Recovery Time 16 23 ns
(1) Specified by design
CSD87588N Thermal_Max.gif
 Max RθJA = 70°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD87588N Thermal_Min.gif
 Max RθJA = 170°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise.The Typical Power Block System Characteristic curves Figure 3 and Figure 4 are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
CSD87588N graph_01_SLPS384_F.png
Figure 1. Power Loss vs Output Current
CSD87588N graph_03_SLPS384_F.png
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87588N graph_02_SLPS384_F.png
Figure 2. Normalized Power Loss vs Temperature
CSD87588N graph_04_SLPS384_F.png
Figure 4. Typical Safe Operating Area
CSD87588N graph_05_SLPS384_F2.png
Figure 5. Normalized Power Loss vs Switching Frequency
CSD87588N graph_07_SLPS384_F.png
Figure 7. Normalized Power Loss vs Output Voltage
CSD87588N graph_06_SLPS384_F.png
Figure 6. Normalized Power Loss vs Input Voltage
CSD87588N graph_08_SLPS384_F.png
Figure 8. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87588N graph_09_SLPS384_F.png
Figure 9. Control MOSFET Saturation
CSD87588N graph_11_SLPS384_F2.png
Figure 11. Control MOSFET Transfer
CSD87588N graph_13_SLPS384_F2.png
Figure 13. Control MOSFET Gate Charge
CSD87588N graph_15_SLPS384D.png
Figure 15. Control MOSFET Capacitance
CSD87588N graph_17_SLPS384_F.png
Figure 17. Control MOSFET VGS(th)
CSD87588N graph_19_SLPS384_F.png
Figure 19. Control MOSFET RDS(on) vs VGS
CSD87588N graph_21_SLPS384_F.png
Figure 21. Control MOSFET Normalized RDS(on)
CSD87588N graph_23_SLPS384_F.png
Figure 23. Control MOSFET Body Diode
CSD87588N graph_25_SLPS384_F.png
Figure 25. Control MOSFET Unclamped Inductive Switching
CSD87588N graph_10_SLPS384_F.png
Figure 10. Sync MOSFET Saturation
CSD87588N graph_12_SLPS384_F.png
Figure 12. Sync MOSFET Transfer
CSD87588N graph_14_SLPS384_F.png
Figure 14. Sync MOSFET Gate Charge
CSD87588N graph_16_SLPS384D.png
Figure 16. Sync MOSFET Capacitance
CSD87588N graph_18_SLPS384_F.png
Figure 18. Sync MOSFET VGS(th)
CSD87588N graph_20_SLPS384_F.png
Figure 20. Sync MOSFET RDS(on) vs VGS
CSD87588N graph_22_SLPS384_F.png
Figure 22. Sync MOSFET Normalized RDS(on)
CSD87588N graph_24_SLPS384_F.png
Figure 24. Sync MOSFET Body Diode
CSD87588N graph_26_SLPS384_F.png
Figure 26. Sync MOSFET Unclamped Inductive Switching

6 Application and Implementation

6.1 Application Information

The CSD87588N NexFET power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored toward a more systems-centric environment. System-level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application.

6.1.1 Power Loss Curves

MOSFET-centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. To simplify the design process for engineers, TI has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87588N as a function of load current. This curve is measured by configuring and running the CSD87588N as it would be in the final application (see Figure 27). The measured power loss is the CSD87588N loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions.

6.1.2 Safe Operating Curves (SOA)

The SOA curves in the CSD87588N data sheet provide guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness.

6.1.3 Normalized Curves

The normalized curves in the CSD87588N data sheet provides guidance on the Power Loss and SOA adjustments based on their application-specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power loss and the secondary y-axis is the change in system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve.

CSD87588N Typical_App_Circ2.gifFigure 27. Typical Application

6.1.4 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions.

6.1.4.1 Design Example

Operating Conditions:

  • Output Current = 15 A
  • Input Voltage = 7 V
  • Output Voltage = 1 V
  • Switching Frequency = 800 kHz
  • Inductor = 0.2 µH

6.1.4.2 Calculating Power Loss

  • Power Loss at 15 A = 2.75 W (Figure 1)
  • Normalized Power Loss for input voltage ≈ 1.03 (Figure 6)
  • Normalized Power Loss for output voltage ≈ 0.94 (Figure 7)
  • Normalized Power Loss for switching frequency ≈ 1.08 (Figure 5)
  • Normalized Power Loss for output inductor ≈ 1.03 (Figure 8)
  • Final calculated Power Loss = 2.75 W × 1.05 × 0.95 × 1.05 × 1.05 ≈ 3.02 W

6.1.4.3 Calculating SOA Adjustments

  • SOA adjustment for input voltage ≈ 0.3ºC (Figure 6)
  • SOA adjustment for output voltage ≈ –0.5ºC (Figure 7)
  • SOA adjustment for switching frequency ≈ 0.7ºC (Figure 5)
  • SOA adjustment for output inductor ≈ 0.3ºC (Figure 8)
  • Final calculated SOA adjustment = 0.3 + (–0.5) + 0.7 + 0.3 ≈ 0.8ºC

In the previous design example, the estimated power loss of the CSD87588N would increase to 3.02 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 0.8ºC. Figure 28 graphically shows how the SOA curve would be adjusted accordingly.

  1. Start by drawing a horizontal line from the application current to the SOA curve.
  2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
  3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 0.8ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.

CSD87588N soa.pngFigure 28. Power Block SOA

7 Layout

7.1 Layout Guidelines

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The following sections provide a brief description on how to address each parameter.

7.1.1 Electrical Performance

The CSD87588N has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD87588N device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29). The example in Figure 29 uses 1 x 10 nF 0402 25 V and 4 x 10 μF 1206 25 V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C21, C5, C8, C19, and C18 should follow in order.
  • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87588N VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. See Figure 29. (1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7.1.2 Thermal Performance

The CSD87588N has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole and a 16 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

7.2 Layout Example

CSD87588N Thermal_Performance_Image.pngFigure 29. Recommended PCB Layout (Top Down View)

8 Device and Documentation Support

8.1 Trademarks

NexFET is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

8.2 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 CSD87588N Package Dimensions

CSD87588N mechanical_drawing2_updated.png

Pin Configuration

Position Designation
Pin 1 TG
Pin 2 VIN
Pin 3 PGND
Pin 4 BG
Pin 5 VSW

9.2 Land Pattern Recommendation

CSD87588N Recommended_PCB_Pattern.png

9.3 Stencil Recommendation (100 µm)

CSD87588N Recommended_100um_Stencil2_Updated.png

9.4 Stencil Recommendation (125 µm)

CSD87588N Recommended_125um_Stencil2.png


For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques.

9.5 Pin Drawing

CSD87588N Pin_Drawing.png

9.6 CSD87588N Embossed Carrier Tape Dimensions

CSD87588N Tape_and_Reel.png
1. Pin 1 is oriented in the top-left quadrant of the tape enclosure (closest to the carrier tape sprocket holes).

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