SNAS407H August   2007  – April 2015 DAC128S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Serial Interface
      5. 8.3.5 Daisy-Chain Operation
      6. 8.3.6 DAC Input Data Update Mechanism
      7. 8.3.7 Power-On Reset
      8. 8.3.8 Transfer Characteristic
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Programming the DAC128S085
        1. 8.5.1.1 Updating DAC Outputs Simultaneously
        2. 8.5.1.2 Updating DAC Outputs Independently
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using References as Power Supplies
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Specification Definitions
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Ensured Monotonicity
  • Low Power Operation
  • Rail-to-Rail Voltage Output
  • Daisy-Chain Capability
  • Power-on Reset to 0 V
  • Simultaneous Output Updating
  • Individual Channel Power-Down Capability
  • Wide Power Supply Range (2.7 V to 5.5 V)
  • Dual Reference Voltages With Range of 0.5 V to VA
  • Operating Temperature Range of −40°C to 125°C
  • Smallest Package in the Industry
  • Resolution 12 Bits
  • INL ±8 LSB (Maximum)
  • DNL 0.75 / −0.4 LSB (Maximum)
  • Settling Time 8.5 μs (Maximum)
  • Zero Code Error 15 mV (Maximum)
  • Full-Scale Error −0.75 %FSR (Maximum)
  • Supply Power
    • 1.95 mW (3 V) / 4.85 mW (5 V) Typical
    • Power Down 0.3 μW (3 V) / 1 μW (5 V) Typical

2 Applications

  • Battery-Powered Instruments
  • Digital Gain and Offset Adjustment
  • Programmable Voltage and Current Sources
  • Programmable Attenuators
  • Voltage Reference for ADCs
  • Sensor Supply Voltage
  • Range Detectors

3 Description

The DAC128S085 is a full-featured, general-purpose OCTAL 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes 1.95 mW at 3 V and 4.85 mW at 5 V. The DAC128S085 is packaged in a 16-lead WQFN package and a 16-lead TSSOP package. The WQFN package makes the DAC128S085 the smallest OCTAL DAC in its class. The on-chip output amplifiers allow rail-to-rail output swing, and the 3-wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25-MHz clock rates at supply voltages in the 2.7-V to 3.6-V range. The serial interface is compatible with standard SPI™, QSPI, MICROWIRE, and DSP interfaces. The DAC128S085 also offers daisy-chain operation, where an unlimited number of DAC128S085s can be updated simultaneously using a single serial interface.

There are two references for the DAC128S085. One reference input serves channels A through D, while the other reference serves channels E through H. Each reference can be set independently between 0.5 V and VA, providing the widest possible output dynamic range. The DAC128S085 has a 16-bit input shift register that controls the mode of operation, the power-down condition, and the register/output value of the DAC channels. All eight DAC outputs can be updated simultaneously or individually.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC128S085 TSSOP (16) 5.00 mm × 4.4 mm
WQFN (16) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

DAC128S085 Graphic_SNAS407.gif