DLPS168C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • DLPC6540 controller using the DLP471TP digital micromirror device (DMD) supports
    • Up to 4K UHD at 60 Hz
    • Up to 1080p at 240 Hz (2D) and 120 Hz (3D)
  • Provides single V-by-One® HS video input port with one, two, four, or eight lanes
    • Up to 600-MHz pixel clock support
    • Up to 3.0-Gbps input transmission rate
  • Input formats supported
    • RGB, YCbCr, and ICtCp
    • 4:4:4, 4:2:2, 4:2:0
  • Internal Arm® Cortex®R4F processor with FPU
    • 88 configurable GPIOs
    • Programmable PWM generator
    • Programmable capture and delay timers
    • USB 2.0 high-speed OTG controller
    • SPI primary/secondary controllers
    • I2C primary/secondary controllers
    • UART and interrupt controllers
  • Warping engine
    • Improved 1D, 2D, and 3D keystone correction
    • Optical distortion correction (radial and lateral color distortion; for example, for short throw)
    • Warping (multipoint manual warp and full warp map access 62 × 32 points)
    • Blending (manual blending and full blending map access 63 × 32 points)
  • Additional image processing
    • DynamicBlack
    • TI DLP® BrilliantColor™ Technology
    • HDR10 (PQ and HLG) support
    • Frame rate conversion
    • Color coordinate adjustment
    • White color temperature adjustment
    • Programmable degamma
    • Spatial-temporal multiplexing
    • Integrated support for 3-D display
  • Splash screen display and capture
  • Integrated 2G-bit frame memory eliminates need for external high-speed memory
  • External memory support
    • Parallel flash for µP and PWM sequences
    • Secondary flash for splash capture, warping
  • System control
    • DMD power and reset driver control
    • DMD horizontal and vertical image flip
  • JTAG boundary scan test support