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  • DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

    • SLOS866F May   2014  – March 2018 DRV2604L

      PRODUCTION DATA.  

  • CONTENTS
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  • DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Setup for Graphs
      1. 7.1.1 Default Test Conditions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Support for ERM and LRA Actuators
      2. 8.3.2  Smart-Loop Architecture
        1. 8.3.2.1 Auto-Resonance Engine for LRA
        2. 8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA
        3. 8.3.2.3 Automatic Switch to Open-Loop for LRA
        4. 8.3.2.4 Automatic Overdrive and Braking
          1. 8.3.2.4.1 Startup Boost
          2. 8.3.2.4.2 Brake Factor
          3. 8.3.2.4.3 Brake Stabilizer
        5. 8.3.2.5 Automatic Level Calibration
          1. 8.3.2.5.1 Automatic Compensation for Resistive Losses
          2. 8.3.2.5.2 Automatic Back-EMF Normalization
          3. 8.3.2.5.3 Calibration Time Adjustment
          4. 8.3.2.5.4 Loop-Gain Control
          5. 8.3.2.5.5 Back-EMF Gain Control
        6. 8.3.2.6 Actuator Diagnostics
        7. 8.3.2.7 Automatic Re-Synchronization
      3. 8.3.3  Open-Loop Operation for LRA
      4. 8.3.4  Open-Loop Operation for ERM
      5. 8.3.5  Flexible Front-End Interface
        1. 8.3.5.1 PWM Interface
        2. 8.3.5.2 Internal Memory Interface
          1. 8.3.5.2.1 Waveform Sequencer
          2. 8.3.5.2.2 Library Parameterization
        3. 8.3.5.3 Real-Time Playback (RTP) Interface
        4. 8.3.5.4 Analog Input Interface
        5. 8.3.5.5 Input Trigger Option
          1. 8.3.5.5.1 I2C Trigger
          2. 8.3.5.5.2 Edge Trigger
          3. 8.3.5.5.3 Level Trigger
        6. 8.3.5.6 Noise Gate Control
      6. 8.3.6  Edge Rate Control
      7. 8.3.7  Constant Vibration Strength
      8. 8.3.8  Battery Voltage Reporting
      9. 8.3.9  One-Time Programmable (OTP) Memory for Configuration
      10. 8.3.10 Low-Power Standby
      11. 8.3.11 I2C Watchdog Timer
      12. 8.3.12 Device Protection
        1. 8.3.12.1 Thermal Protection
        2. 8.3.12.2 Overcurrent Protection of the Actuator
        3. 8.3.12.3 Overcurrent Protection of the Regulator
        4. 8.3.12.4 Brownout Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
        1. 8.4.1.1 Operation With VDD < 2 V (Minimum VDD)
        2. 8.4.1.2 Operation With VDD > 5.5 V (Absolute Maximum VDD)
        3. 8.4.1.3 Operation With EN Control
        4. 8.4.1.4 Operation With STANDBY Control
        5. 8.4.1.5 Operation With DEV_RESET Control
        6. 8.4.1.6 Operation in the Active State
      2. 8.4.2 Changing Modes of Operation
      3. 8.4.3 Operation of the GO Bit
      4. 8.4.4 Operation During Exceptional Conditions
        1. 8.4.4.1 Operation With No Actuator Attached
        2. 8.4.4.2 Operation With a Non-Moving Actuator Attached
        3. 8.4.4.3 Operation With a Short at REG Pin
        4. 8.4.4.4 Operation With a Short at OUT+, OUT–, or Both
    5. 8.5 Programming
      1. 8.5.1 Auto-Resonance Engine Programming for the LRA
        1. 8.5.1.1 Drive-Time Programming
        2. 8.5.1.2 Current-Dissipation Time Programming
        3. 8.5.1.3 Blanking Time Programming
        4. 8.5.1.4 Zero-Crossing Detect-Time Programming
      2. 8.5.2 Automatic-Level Calibration Programming
        1. 8.5.2.1 Rated Voltage Programming
        2. 8.5.2.2 Overdrive Voltage-Clamp Programming
      3. 8.5.3 I2C Interface
        1. 8.5.3.1 General I2C Operation
        2. 8.5.3.2 Single-Byte and Multiple-Byte Transfers
        3. 8.5.3.3 Single-Byte Write
        4. 8.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
        5. 8.5.3.5 Single-Byte Read
        6. 8.5.3.6 Multiple-Byte Read
      4. 8.5.4 Programming for Open-Loop Operation
        1. 8.5.4.1 Programming for ERM Open-Loop Operation
        2. 8.5.4.2 Programming for LRA Open-Loop Operation
      5. 8.5.5 Programming for Closed-Loop Operation
      6. 8.5.6 Auto Calibration Procedure
      7. 8.5.7 Programming On-Chip OTP Memory
      8. 8.5.8 Waveform Playback Programming
        1. 8.5.8.1 Data Formats for Waveform Playback
          1. 8.5.8.1.1 Open-Loop Mode
          2. 8.5.8.1.2 Closed-Loop Mode, Unidirectional
          3. 8.5.8.1.3 Closed-Loop Mode, Bidirectional
        2. 8.5.8.2 Waveform Setup and Playback
          1. 8.5.8.2.1 Waveform Playback Using RTP Mode
          2. 8.5.8.2.2 Waveform Playback Using the Analog-Input Mode
          3. 8.5.8.2.3 Waveform Playback Using PWM Mode
          4. 8.5.8.2.4 Loading Data to RAM
            1. 8.5.8.2.4.1 Header Format
            2. 8.5.8.2.4.2 RAM Waveform Data Format
          5. 8.5.8.2.5 Waveform Sequencer
          6. 8.5.8.2.6 Waveform Triggers
    6. 8.6 Register Map
      1. 8.6.1  Status (Address: 0x00)
        1. Table 3. Status Register Field Descriptions
      2. 8.6.2  Mode (Address: 0x01)
        1. Table 4. Mode Register Field Descriptions
      3. 8.6.3  Real-Time Playback Input (Address: 0x02)
        1. Table 5. Real-Time Playback Input Register Field Descriptions
      4. 8.6.4  HI_Z (Address: 0x03)
        1. Table 6. HI_Z Register Field Descriptions
      5. 8.6.5  Waveform Sequencer (Address: 0x04 to 0x0B)
        1. Table 7. Waveform Sequencer Register Field Descriptions
      6. 8.6.6  GO (Address: 0x0C)
        1. Table 8. GO Register Field Descriptions
      7. 8.6.7  Overdrive Time Offset (Address: 0x0D)
        1. Table 9. Overdrive Time Offset Register Field Descriptions
      8. 8.6.8  Sustain Time Offset, Positive (Address: 0x0E)
        1. Table 10. Sustain Time Offset, Positive Register Field Descriptions
      9. 8.6.9  Sustain Time Offset, Negative (Address: 0x0F)
        1. Table 11. Sustain Time Offset, Negative Register Field Descriptions
      10. 8.6.10 Brake Time Offset (Address: 0x10)
        1. Table 12. Brake Time Offset Register Field Descriptions
      11. 8.6.11 Rated Voltage (Address: 0x16)
        1. Table 13. Rated Voltage Register Field Descriptions
      12. 8.6.12 Overdrive Clamp Voltage (Address: 0x17)
        1. Table 14. Overdrive Clamp Voltage Register Field Descriptions
      13. 8.6.13 Auto-Calibration Compensation Result (Address: 0x18)
        1. Table 15. Auto-Calibration Compensation-Result Register Field Descriptions
      14. 8.6.14 Auto-Calibration Back-EMF Result (Address: 0x19)
        1. Table 16. Auto-Calibration Back-EMF Result Register Field Descriptions
      15. 8.6.15 Feedback Control (Address: 0x1A)
        1. Table 17. Feedback Control Register Field Descriptions
      16. 8.6.16 Control1 (Address: 0x1B)
        1. Table 18. Control1 Register Field Descriptions
      17. 8.6.17 Control2 (Address: 0x1C)
        1. Table 19. Control2 Register Field Descriptions
      18. 8.6.18 Control3 (Address: 0x1D)
        1. Table 20. Control3 Register Field Descriptions
      19. 8.6.19 Control4 (Address: 0x1E)
        1. Table 21. Control4 Register Field Descriptions
      20. 8.6.20 Control5 (Address: 0x1F)
        1. Table 22. Control5 Register Field Descriptions
      21. 8.6.21 LRA Open Loop Period (Address: 0x20)
        1. Table 23. LRA Open Loop Period Register Field Descriptions
      22. 8.6.22 V(BAT) Voltage Monitor (Address: 0x21)
        1. Table 24. V(BAT) Voltage-Monitor Register Field Descriptions
      23. 8.6.23 LRA Resonance Period (Address: 0x22)
        1. Table 25. LRA Resonance-Period Register Field Descriptions
      24. 8.6.24 RAM-Address Upper Byte (Address: 0xFD)
        1. Table 26. RAM-Address Upper-Byte Register Field Descriptions
      25. 8.6.25 RAM-Address Lower Byte (Address: 0xFE)
        1. Table 27. RAM Address Lower Byte Register Field Descriptions
      26. 8.6.26 RAM Data Byte (Address: 0xFF)
        1. Table 28. RAM-Data Byte Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Actuator Selection
          1. 9.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)
          2. 9.2.2.1.2 Linear Resonance Actuators (LRA)
            1. 9.2.2.1.2.1 Auto-Resonance Engine for LRA
        2. 9.2.2.2 Capacitor Selection
        3. 9.2.2.3 Interface Selection
        4. 9.2.2.4 Power Supply Selection
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Initialization Procedure
      2. 9.3.2 Typical Usage Examples
        1. 9.3.2.1 Play a Waveform or Waveform Sequence from the RAM Waveform Memory
        2. 9.3.2.2 Play a Real-Time Playback (RTP) Waveform
        3. 9.3.2.3 Play a PWM or Analog Input Waveform
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Trace Width
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DGS|10
    • MPDS035C
  • YZF|9
    • MXBG027N
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slos866f_oa
  • slos866f_pm
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DATA SHEET

DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM with Internal Memory and Smart-Loop Architecture

1 Features

  • Flexible Haptic and Vibration Driver
    • LRA (Linear Resonance Actuator)
    • ERM (Eccentric Rotating Mass)
  • I2C-Controlled Digital Playback Engine
    • Waveform Sequencer and Trigger
    • Real-Time Playback Mode through I2C
    • Internal RAM for Customized Waveforms
    • I2C Dual-Mode Drive (Open and Closed Loop)
  • Smart-Loop Architecture (Patent Pending Control Algorithm)
    • Automatic Overdrive and Braking
    • Automatic Resonance Tracking and Reporting (LRA Only)
    • Automatic Actuator Diagnostic
    • Automatic Level Calibration
    • Wide Support for Actuator Models
  • Immersion TouchSense® 3000 Compatible
  • Drive Compensation Over Battery Discharge
  • Wide Voltage Operation (2 V to 5.2 V)
  • Efficient Differential Switching Output Drive
  • PWM Input with 0% to 100% Duty-Cycle Control Range
  • Hardware Trigger Input
  • Fast Startup Time
  • 1.8-V Compatible, VDD-Tolerant Digital Interface

2 Applications

  • Mobile Phones
  • Tablets

3 Description

The DRV2604L device is a low-voltage haptic driver that provides a closed-loop actuator-control system for high-quality tactile feedback for ERM and LRA. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time and is accessible through a shared I2C compatible bus or PWM input signal.

The DRV2604L device includes enough integrated RAM to allow the user to pre-load over 100 customized smart-loop architecture waveforms. These waveforms can be instantly played back through I2C or optionally triggered through a hardware trigger terminal.

Additionally, the real-time playback mode allows the host processor to bypass the memory playback engine and play waveforms directly from the host through I2C.

The smart-loop architecture inside the DRV2604L device allows simple auto-resonant drive for the LRA as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. The smart-loop architecture creates a simplified input waveform interface as well as reliable motor control and consistent motor performance. The DRV2604L device also features automatic transition to an open-loop system in the event that an LRA actuator is not generating a valid back-EMF voltage. When the LRA generates a valid back-EMF voltage, the DRV2604L device automatically synchronizes with the LRA. The DRV2604L also allows for open-loop driving through the use of internally-generated PWM.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (MAX)
DRV2604L DSBGA (9) 1.50 mm × 1.50 mm
DRV2604L VSSOP (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

DRV2604L simplifiedSchematic_slos866.gif

4 Revision History

Changes from E Revision (August 2016) to F Revision

  • Changed the DEFAULT value for bit 5-4 of Table 19 From: 1 To 3 Go
  • Changed the DEFAULT value for bit 3-2 of Table 19 From: 2 To 1 Go
  • Changed the DEFAULT value for bit 1-0 of Table 19 From: 2 To 1 Go
  • Changed the typical value of C(VDD) in Table 29 From: 0.1 µF To: 1 µFGo

Changes from D Revision (June 2015) to E Revision

  • Table 2, changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDRGo
  • Status (Address: 0x00), changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDRGo

Changes from C Revision (September 2014) to D Revision

  • Released full version of the data sheet Go

5 Pin Configuration and Functions

YZF Package
9-Pin DSBGA With 0.5-mm Pitch
(Top View)

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
A1 EN I Device enable
A2 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required.
A3 OUT+ O Positive haptic driver differential output
B1 IN/TRIG I Multi-mode Input. I2C selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND
B2 SDA I/O I2C data
B3 GND P Supply ground
C1 SCL I I2C clock
C3 OUT– O Negative haptic-driver differential output
C2 VDD P Supply input (2 to 5.2 V). A 1-µF capacitor is required.
(1) I = input, O = output, I/O = input and output, P = power
DGS Package
10-Pin VSSOP
(Top View)

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor required
2 SCL I I2C clock
3 SDA I/O I2C data
4 IN/TRIG I Multi-mode Input. I2C is selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND
5 EN I Device enable
6 VDD/NC P Optional supply input. This pin should be tied to VDD or left floating.
7 OUT+ O Positive haptic driver differential output
8 GND P Supply ground
9 OUT– O Negative haptic driver differential output
10 VDD P Supply Input (2 V to 5.2 V). A 1-µF capacitor is required.
(1) I = input, O = output, I/O = input and output, P = power

 
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