Die temperature monitoring on IPROPI (SPI only)
Over temperature warning (SPI only)
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The DRV8263-Q1 is a wide-voltage, high-power fully integrated H-bridge driver for 24V and 48V automotive applications. Designed in a BiCMOS high-power process technology node, this device in a power package offers excellent power handling and thermal capability while providing compact package size, ease of layout, EMI control, accurate current sense, robustness, and diagnostic capability.
The device integrates a N-channel H-bridge, charge pump, high-side current sensing with regulation, current proportional output, and protection circuitry. The integrated sensing uses a current mirror, removing the need for shunt resistors, saving board area, and reducing system cost. A low-power sleep mode is provided to achieve low quiescent current.
The device offers voltage monitoring and load diagnostics, as well as protection features against overcurrent and overtemperature. Fault conditions are indicated on the nFAULT pin. It is available in two variants: HW interface and SPI interface. The SPI variant offers more flexibility in device configuration and fault observability.
PART NUMBER | INTERFACE | PACKAGE SIZE2 |
---|---|---|
DRV8263HQVAKRQ1 | HW | VQFN-HR (15) (3.5mm x 6mm) |
DRV8263SQVAKRQ1 | SPI | VQFN-HR (15) (3.5mm x 6mm) |
Table 4-1 summarizes the RON and package differences between devices in the DRV8X6X-Q1 family.
PART NUMBER(1) | Configuration | (LS + HS) RON | IOUT MAX | PACKAGE | BODY SIZE | Interface |
---|---|---|---|---|---|---|
DRV8262-Q1 | 1 or 2 H-bridge | 50mΩ or 100mΩ | 16A or 8A | HTSSOP (44) | 14 mm X 6.1 mm | HW |
DRV8962-Q1 | 4 Half-bridge | 100mΩ | 8A | HTSSOP (44) | 14 mm X 6.1 mm | HW |
DRV8263-Q1 | 1 H-bridge | 85mΩ | 29A | VQFN-HR (15) | 3.5 mm X 6 mm | HW, SPI |
DRV8163-Q1 | 1 Half-bridge | 43mΩ | 40A | VQFN-HR (15) | 3.5 mm X 6 mm | HW, SPI |
Table 4-2 summarizes the feature differences between the SPI and HW interface variants in the DRV8263-Q1. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback, and additional features.
FUNCTION | HW Variant | SPI Variant |
---|---|---|
Bridge control | Pin only | Individual pin "and/or" register bit with pin status indication (Refer Register Pin control) |
Clear fault command | Reset pulse on nSLEEP pin | SPI CLR_FAULT command |
Over current protection (OCP) | Fixed at the highest setting | 4 choices for thresholds, 4 choices for filter time |
5 levels with disable & fixed TOFF time | 7 levels with disable & indication, with programmable TOFF time | |
Individual fault reaction configuration between retry or latched behavior | Not supported, either all latched or all retry | Supported |
Detailed fault logging and device status feedback | Not supported, nFAULT pin monitoring necessary | Supported, nFAULT pin monitoring optional |
VM over voltage | Not supported | Supported |
On-state (Active) diagnostics | Not supported | Supported for high-side loads |
Spread spectrum clocking (SSC) | Not supported | Supported |
Additional driver states in PWM mode | Not supported | Supported |
Hi-Z for individual half-bridge in Independent mode | Not supported | Supported (SPI register only) |
Not supported | ||
Not supported |
Device | Package Symbolization | DEVICE_ID Register |
---|---|---|
DRV8262-Q1 | 8262 | Not applicable |
DRV8962-Q1 | 8962 | Not applicable |
DRV8263H-Q1 | 8263H | Not applicable |
DRV8163H-Q1 | 8163H | Not applicable |
DRV8263S-Q1 | 8263S | 0 x 34 |
DRV8163S-Q1 | 8163S | 0 x 3C |
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | nFAULT | OD | Fault indication to the controller. |
2 | IPROPI | I/O | Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration section. |
3 | nSLEEP | I | Controller input pin for SLEEP . For details, see the Bridge Control section. |
4 | VM | P | Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1µF ceramic capacitor and a bulk capacitor. |
5 | OUT2 | P | Half-bridge output 2. Connect these pins together to the motor or load. |
6 | GND | G | Ground pin |
7 | OUT1 | P | Half-bridge output 1. Connect these pins together to the motor or load. |
8 | DRVOFF | I | Controller input pin for bridge Hi-Z. For details, see the Bridge Control section. |
9 | EN/IN1 | I | Controller input pin for bridge operation. For details, see the Bridge Control section. |
10 | PH/IN2 | I | Controller input pin for bridge operation. For details, see the Bridge Control section. |
11 | VDD | P | Logic power supply to the device. |
12 | DIAG | I | Device configuration pin for load type indication and fault reaction configuration. For details, refer to DIAG in the Device Configuration section. |
13 | SR | I | Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device Configuration section. |
14 | ITRIP | I | Device configuration pin for ITRIP level for high-side current limiting. For details, refer to ITRIP in the Device Configuration section. |
15 | MODE | I | Device configuration pin for MODE. For details, refer to the Bridge Control section. |
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | nFAULT | OD | Fault indication to the controller. |
2 | IPROPI | I/O | Multi-purpose pin. Provides driver load current analog feedback or analog voltage proportional to die temperature. For details, refer to IPROPI in the Device Configuration section. |
3 | nSLEEP | I | Controller input pin for SLEEP . For details, see the Bridge Control section. |
4 | VM | P | Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1µF ceramic capacitor and a bulk capacitor. |
5 | OUT2 | P | Half-bridge output 2. Connect these pins together to the motor or load. |
6 | GND | G | Ground pin |
7 | OUT1 | P | Half-bridge output 1. Connect these pins together to the motor or load. |
8 | DRVOFF | I | Controller input pin for bridge Hi-Z. For details, see the Bridge Control section. |
9 | EN/IN1 | I | Controller input pin for bridge operation. For details, see the Bridge Control section. |
10 | PH/IN2 | I | Controller input pin for bridge operation. For details, see the Bridge Control section. |
11 | VDD | P | Logic power supply to the device. |
12 | nSCS | I | SPI - Chip Select. An active low on this pin enables the serial interface communication. |
13 | SCLK | I | SPI - Serial Clock input. |
14 | SDI | I | SPI - Serial Data Input. Data is captured at the falling edge of SCLK. |
15 | SDO | PP | SPI - Serial Data Output. Data is updated at the rising edge of SCLK. |