SNLS732 February   2023 DS160PR1601

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Control and Configuration Interface
      1. 7.3.1 Pin Configurations for Lanes
        1. 7.3.1.1 Five-Level Control Inputs
      2. 7.3.2 SMBUS/I2C Register Control Interface
      3. 7.3.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
    4. 7.4 Feature Description
      1. 7.4.1 Linear Equalization
      2. 7.4.2 Flat-Gain
      3. 7.4.3 Analog EyeScan
      4. 7.4.4 Receiver Detect State Machine
      5. 7.4.5 Integrated Capacitors
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active PCIe Mode
      2. 7.5.2 Active Buffer Mode
      3. 7.5.3 Standby Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 16-lane linear redriver supporting PCIe 4.0, and UPI 2.0
  • Supports data rates up to 16-Gbps
  • P2P with Intel retimer common footprint
  • 64 integrated AC coupling capacitors on TX pins inside package saving board space
  • CTLE boosts of 16 dB at 8 GHz
  • Analog EyeScan to aid redriver tuning, debug and remote monitoring
  • Ultra-low latency of 130 ps
  • Low additive random jitter of 100 fs for PRBS data
  • Excellent RX/TX return loss of −13 dB at 8 GHz
  • Single 3.3 V supply
  • Low active power of 160 mW/channel
  • I2C/SMBus or EEPROM programming
  • Automatic receiver detection for PCIe use cases
  • Seamless support for PCIe link training
  • Internal voltage regulator provides immunity to supply noise
  • High speed production testing for reliable manufacturing
  • Support for x4, x8, x16 bus width
  • 8.90 mm × 22.80 mm BGA package