SNLS624
September 2018
DSLVDS1048
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
3.1
Application Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Fail-Safe Feature
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Probing LVDS Transmission Lines
9.2.2.2
Threshold
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Power Decoupling Recommendations
11.1.2
Differential Traces
11.1.3
Termination
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|16
MPDS361A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls624_oa
snls624_pm
1
Features
Designed for Signal Rates up to 400 Mbps
Flow-Through Pinout Simplifies PCB Layout
150-ps Channel-to-Channel Skew (Typical)
100-ps Differential Skew (Typical)
2.7-ns Maximum Propagation Delay
3.3-V Power Supply Design
High Impedance LVDS Inputs on Power Down
Low Power Design (40 mW at 3.3-V Static)
Interoperable With Existing 5-V LVDS Drivers
Accepts Small Swing (350 mV Typical) Differential Signal Levels
Supports Input Failsafe
Open, Short, and Terminated
0 V to −100 mV Threshold Region
Operating Temperature Range: –40°C to +85°C
Meets or Exceeds ANSI/TIA/EIA-644 Standard
Available in TSSOP Package