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  • SN74AUP1G00 Low-Power Single 2-Input Positive-NAND Gate

    • SCES604J SEPTEMBER   2004  – December 2016 SN74AUP1G00

      PRODUCTION DATA.  

  • CONTENTS
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  • SN74AUP1G00 Low-Power Single 2-Input Positive-NAND Gate
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 5 pF
    7. 6.7  Switching Characteristics, CL = 10 pF
    8. 6.8  Switching Characteristics, CL = 15 pF
    9. 6.9  Switching Characteristics, CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

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DATA SHEET

SN74AUP1G00 Low-Power Single 2-Input Positive-NAND Gate

1 Features

  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.8 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II

2 Applications

  • ATCA Solutions
  • Active Noise Cancellation (ANC)
  • Barcode Scanner
  • Blood Pressure Monitor
  • CPAP Machine
  • Cable Solutions
  • DLP 3D Machine Vision, Hyperspectral Imaging, Optical Networking, and Spectroscopy
  • E-Book
  • Embedded PC
  • Field Transmitter: Temperature or Pressure Sensor
  • Fingerprint Biometrics
  • HVAC: Heating, Ventilating, and Air Conditioning
  • Network-Attached Storage (NAS)
  • Server Motherboard and PSU
  • Software Defined Radio (SDR)
  • TV: High-Definition (HDTV), LCD, and Digital
  • Video Communications System
  • Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card
  • X-ray: Baggage Scanner, Medical, and Dental

3 Description

This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G00DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUP1G00DCK SC70 (5) 2.00 mm × 1.25 mm
SN74AUP1G00DRL SOT (5) 1.60 mm × 1.20 mm
SN74AUP1G00DRY SON (6) 1.45 mm × 1.00 mm
SN74AUP1G00DSF SON (6) 1.00 mm × 1.00 mm
SN74AUP1G00YFP DSBGA (6) 1.00 mm × 1.40 mm
SN74AUP1G00YZP DSBGA (5) 1.37 mm × 0.87 mm
SN74AUP1G00DPW X2SON (5) 0.80 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74AUP1G00 lo_dgm_ces604.gif

4 Revision History

Changes from I Revision (June 2014) to J Revision

  • Changed X2SON package pin count from: "(4)" to: "(5)"Go
  • Added DSF (SON) (6), YFP (DSBGA) (6), and YZP (DSBGA) (5) packages to Device InformationGo
  • Changed pinout images with new diagramsGo
  • Changed Pin Functions table to Pin Functions — DBV, DCK, DRL, DPW, DRY, and DSF and Pin Functions — YZP and YFP tablesGo
  • Added missing pinout information to Pin Functions table Go
  • Added Junction temperature, TJ Go
  • Changed Handling Ratings table to a ESD Ratings tableGo
  • Changed unit from: "A" to:"µA" for IOL at VCC = 0.8 V Go
  • Added Receiving Notification of Documentation Updates section and Community Resources sectionGo

Changes from H Revision (April 2012) to I Revision

  • Updated document to new TI data sheet format.Go
  • Removed Ordering Information table.Go
  • Updated Ioff in Features. Go
  • Added Applications.Go
  • Added Device Information table. Go
  • Added DPW PackageGo
  • Added Handling Ratings table.Go
  • Added Thermal Information table.Go
  • Added Typical Characteristics.Go

Changes from G Revision (March 2010) to H Revision

  • Corrected the MIN Value for 1.2 V per available characterization data.Go

5 Pin Configuration and Functions

DBV, DCK, or DRL Package
5-Pin SOT-23, SC70, or SOT
Top View
DRY or DSF Package
6-Pin SON
Top View
N.C. – No internal connection
DPW Package
5-Pin X2SON
Top View

Pin Functions — DBV, DCK, DRL, DPW, DRY, and DSF(1)

PIN I/O DESCRIPTION
NAME DBV, DCK,
DRL		 DPW DRY,
DSF
A 1 2 1 I Input A
B 2 1 2 I Input B
GND 3 3 3 — Ground
N.C. – – 5 — No internal connection
VCC 5 5 6 — Power Pin
Y 4 4 4 O Output Y
(1) See mechanical drawings for dimensions.
YZP Package
5-Pin DSBGA
Bottom View
YFP Package
6-Pin DSBGA
Bottom View
DNU – Do not use

Pin Functions — YZP and YFP(1)

PIN I/O DESCRIPTION
YZP YFP NAME
A1 A1 A I Input A
A2 A2 VCC — Power Pin
B1 B1 B I Input B
– B2 DNU — Do not use
C1 C1 GND — Ground
C2 C2 Y O Output Y
(1) See mechanical drawings for dimensions.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
VI Input voltage (2) –0.5 4.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VO Output voltage range in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 50 mA
IOK Output clamp current VO < 0 50 mA
IO Continuous output current 20 mA
Continuous current through VCC or GND 50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VIH High-level input voltage VCC = 0.8 V VCC V
VCC = 1.1 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VIL Low-level input voltage VCC = 0.8 V 0 V
VCC = 1.1 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VI Input voltage 0 3.6 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 0.8 V –20 µA
VCC = 1.1 V –1.1 mA
VCC = 1.4 V –1.7
VCC = 1.65 –1.9
VCC = 2.3 V –3.1
VCC = 3 V –4
IOL Low-level output current VCC = 0.8 V 20 µA
VCC = 1.1 V 1.1 mA
VCC = 1.4 V 1.7
VCC = 1.65 V 1.9
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TA Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

THERMAL METRIC(1) SN74AUP1G00 UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DPW
(X2SON)		 DRL
(SOT)		 DRY
(SON)		 DSF
(SON)
5 PINS 5 PINS 5 PINS 5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 298.6 314.4 291.8 349.7 554.9 407.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 240.2 128.7 224.2 120.5 385.4 232.0 °C/W
RθJB Junction-to-board thermal resistance 134.6 100.6 245.8 171.4 388.2 306.9 °C/W
ψJT Junction-to-top characterization parameter 114.5 7.1 31.4 10.8 159.0 40.3 °C/W
ψJB Junction-to-board characterization parameter 133.9 99.8 245.6 169.4 384.1 306.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 195.4 n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TA = 25°C TA = –40°C to +85°C UNIT
MIN TYP MAX MIN MAX
VOH IOH = –20 µA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 V
IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.11 1.03
IOH = –1.9 mA 1.65 V 1.32 1.3
IOH = –2.3 mA 2.3 V 2.05 1.97
IOH = –3.1 mA 1.9 1.85
IOH = –2.7 mA 3 V 2.72 2.67
IOH = –4 mA 2.6 2.55
VOL IOL = 20 µA 0.8 V to 3.6 V 0.1 0.1 V
IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31 0.37
IOL = 1.9 mA 1.65 V 0.31 0.35
IOL = 2.3 mA 2.3 V 0.31 0.33
IOL = 3.1 mA 0.44 0.45
IOL = 2.7 mA 3 V 0.31 0.33
IOL = 4 mA 0.44 0.45
II A or
B input		 VI = GND to 3.6 V 0 V to 3.6 V 0.1 0.5 µA
Ioff VI or VO = 0 V to 3.6 V 0 V 0.2 0.6 µA
ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µA
ICC VI = GND or (VCC to 3.6 V),
IO = 0		 0.8 V to 3.6 V 0.5 0.9 µA
ΔICC VI = VCC – 0.6 V(1), IO = 0 3.3 V 40 50 µA
Ci VI = VCC or GND 0 V 1.5 pF
3.6 V 1.5
Co VO = GND 0 V 3 pF
(1) One input at VCC – 0.6 V, other input at VCC or GND.

6.6 Switching Characteristics, CL = 5 pF

over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC TA = 25°C TA = –40°C to +85°C UNIT
MIN TYP MAX MIN MAX
tpd A or B Y 0.8 V 16.6 ns
1.2 V ± 0.1 V 2.6 7 13.8 2.1 17.1
1.5 V ± 0.1 V 2.9 5 9.2 2.9 11.1
1.8 V ± 0.15 V 2 4 7.1 2 9
2.5 V ± 0.2 V 1.3 2.9 4.9 1.3 6.2
3.3 V ± 0.3 V 1 2.4 3.8 1 4.8

6.7 Switching Characteristics, CL = 10 pF

over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC TA = 25°C TA = –40°C to +85°C UNIT
MIN TYP MAX MIN MAX
tpd A or B Y 0.8 V 18.9 ns
1.2 V ± 0.1 V 3.2 8 15.7 3.1 18.8
1.5 V ± 0.1 V 2.9 5.8 10.5 2.9 12.1
1.8 V ± 0.15 V 2 4.7 8.2 2 9.8
2.5 V ± 0.2 V 1.3 3.4 5.7 1.3 6.8
3.3 V ± 0.3 V 1 2.9 4.5 1 5.2

6.8 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC TA = 25°C TA = –40°C to +85°C UNIT
MIN TYP MAX MIN MAX
tpd A or B Y 0.8 V 21.3 ns
1.2 V ± 0.1 V 3.6 9 17.3 3.1 21.5
1.5 V ± 0.1 V 2.9 6.5 11.6 2.9 14
1.8 V ± 0.15 V 2 5.3 9.2 2 11.4
2.5 V ± 0.2 V 1.3 3.9 6.4 1.3 8
3.3 V ± 0.3 V 1 3.3 5.1 1 6.4

6.9 Switching Characteristics, CL = 30 pF

over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC TA = 25°C TA = –40°C to +85°C UNIT
MIN TYP MAX MIN MAX
tpd A or B Y 0.8 V 28.4 ns
1.2 V ± 0.1 V 4.9 11.9 21.9 4.4 27.1
1.5 V ± 0.1 V 2.9 8.6 14.7 2.9 17.7
1.8 V ± 0.15 V 2 7.1 11.5 2 14.2
2.5 V ± 0.2 V 1.3 5.3 8.1 1.3 10
3.3 V ± 0.3 V 1 4.5 6.5 1 8

6.10 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance f = 10 MHz 0.8 V 4 pF
1.2 V ± 0.1 V 4
1.5 V ± 0.1 V 4
1.8 V ± 0.15 V 4
2.5 V ± 0.2 V 4
3.3 V ± 0.3 V 4

6.11 Typical Characteristics

SN74AUP1G00 D001_SCES604.gif Figure 1. TDP vs VCC
SN74AUP1G00 D002_SCES604.gif Figure 2. TPD vs Temperature

7 Parameter Measurement Information

7.1 Propagation Delays, Setup and Hold Times, and Pulse Width

SN74AUP1G00 pmi1_ces604.gif Figure 3. Load Circuit and Voltage Waveforms

7.2 Enable and Disable Times

SN74AUP1G00 pmi2_ces604.gif Figure 4. Load Circuit and Voltage Waveforms

8 Detailed Description

8.1 Overview

This is a single 2-input positive-NAND gate that is designed in Texas Instrument’s ultra-low power technology. It performs the Boolean function Y = A × B or Y = A + B in positive logic.

The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live insertion.

8.2 Functional Block Diagram

SN74AUP1G00 lo_dgm_ces604.gif
Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

  • Wide operating VCC range of 0.8 V to 3.6 V
  • 3.6-V I/O tolerant to support down translation
  • Input hysteresis allows slow input transition and better switching noise immunity at the input
  • Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
  • Low noise due to slower edge rates

8.4 Device Functional Modes

Table 1 shows the functional modes of the SN74AUP1G00 device.

Table 1. Function Table

INPUTS OUTPUT
Y
A B
L L H
L H H
H L H
H H L

9 Application and Implementation

9.1 Application Information

The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It has a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive produces slower edges and prevents overshoot and undershoot on the outputs.

9.2 Typical Application

SN74AUP1G00 app_sche_ces604.gif Figure 6. Typical Application Diagram

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

9.2.2 Detailed Design Procedure

  1. Recommended Input conditions:
    • Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions
    • Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions
    • Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid VCC
  2. Recommended output conditions:
    • Load currents should not exceed 20 mA on the output and 50 mA total for the part
    • Outputs should not be pulled above VCC

9.2.3 Application Curves

SN74AUP1G00 fig1_ces604.gif
Figure 7. AUP – The Lowest-Power Family
SN74AUP1G00 fig2_ces604.gif
Figure 8. Excellent Signal Integrity

The AUP family of single gate logic makes excellent translators for the new lower voltage microprocessors that typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that are still powered by 3.3 V to the new uC power levels.

10 Power Supply Recommendations

The power supply can be any voltage between the Min and Max supply voltage rating located in the Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple-bit logic devices, inputs should never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.

11.2 Layout Example

SN74AUP1G00 layout_ces008.gif Figure 9. Layout Diagram

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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  • OMAP Application Processors: www.ti.com/omap
  • Wireless Connectivity: www.ti.com/wirelessconnectivity

Applications

  • Automotive and Transportation: www.ti.com/automotive
  • Communications and Telecom: www.ti.com/communications
  • Computers and Peripherals: www.ti.com/computers
  • Consumer Electronics: www.ti.com/consumer-apps
  • Energy and Lighting: www.ti.com/energy
  • Industrial: www.ti.com/industrial
  • Medical: www.ti.com/medical
  • Security: www.ti.com/security
  • Space, Avionics and Defense: www.ti.com/space-avionics-defense
  • Video & Imaging: www.ti.com/video

TI E2E Community : e2e.ti.com

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