• 完全静的動作
• バッファ付き入力
• コモン・リセット
• ネガティブ・エッジ・クロッキング
• ファンアウト (全温度範囲にわたって)
  • 標準出力：10 の LSTTL 負荷
  • バス・ドライバ出力：15 の LSTTL 負荷
• 広い動作温度範囲：-55℃～125℃
• 平衡な伝搬遅延と遷移時間
• LSTTL ロジック IC に比べて消費電力を大幅削減
• HC タイプ
  • 2V～6V で動作
  • 優れたノイズ耐性：N_IL = V_CC の 30%、N_IH = V_CC の 30% (VCC = 5V の場合)
• HCT タイプ
  • 4.5V～5.5V で動作
  • LSTTL 入力ロジックと直接互換、
    V_IL = 0.8V (最大値)、V_IH = 2V (最小値)
  • CMOS 入力互換、V_OL、V_OH で I_I ≤ 1µA

HC4024 および HCT4024 は、7 段リップルキャリー・バイナリ・カウンタです。すべてのカウンタ段は、フリップ・フロップです。段の状態は、各入力パルスの負の遷移時に 1 カウント進み、MR ラインが High レベルになると、すべてのカウンタがゼロ状態にリセットされます。すべての入出力はバッファ付きです。

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z_O = 50 Ω, t_t < 6 ns.

For clock inputs, f_max is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

(1) C_L includes probe and test-fixture capacitance.

Figure 6-1 Load Circuit for Push-Pull Outputs

(1) The greater between t_PLH and t_PHL is the same as t_pd.

Figure 6-2 Voltage Waveforms, Propagation Delays for Standard CMOS Inputs

(1) The greater between t_r and t_f is the same as t_t.

Figure 6-3 Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs

(1) The greater between t_PLH and t_PHL is the same as t_pd.

Figure 6-4 Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each V_CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V_CC, whichever makes more sense for the logic function or is more convenient.

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

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