12 ビット DAC63202 および 10 ビット DAC53202 (DACx3202) は、デュアル・チャネル、バッファ付き、電圧出力および電流出力のスマート D/A コンバータ (DAC) のピン互換ファミリです。DACx3202 デバイスは、ハイ・インピーダンスのパワーダウン・モードと、電源オフ状態でのハイ・インピーダンス出力をサポートしています。DAC 出力は、プログラマブルなコンパレータおよび電流シンクとして使用するためのフォース・センス・オプションを備えています。このスマート DAC は、多機能 GPIO、関数生成、NVM によって、プロセッサレス・アプリケーションや設計の再利用を実現できます。I2C、PMBus、SPI インターフェイスを自動的に検出します。また、内部リファレンスを搭載しています。
このスマート DAC は、小型パッケージおよび低消費電力という特長を備えており、電圧マージン設定およびスケーリング、バイアスおよびキャリブレーション用の DC セット・ポイント、波形生成などの用途に最適です。
部品番号 | パッケージ (1) | 本体サイズ (公称) |
---|---|---|
DACx3202 | WQFN (16) | 3.00mm × 3.00mm |
DATE | REVISION | NOTES |
---|---|---|
May 2022 | * | Initial Release |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | FB0 | Input | Voltage
feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current. |
2 | OUT0 | Output | Analog output voltage from DAC channel 0. |
3 | NC | NC | No connection. Leave the pin unconnected. |
4 | NC | NC | No connection. Leave the pin unconnected. |
5 | GPIO/SDO | Input/Output | General-purpose input/output configurable as
LDAC, PD,
PROTECT, RESET, SDO,
and STATUS. For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD. |
6 | SCL/SYNC | Output | I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external pullup resistor. This pin can ramp up before VDD. |
7 | A0/SDI | Input | Address
configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1). For SDI, this pin does not need to be pulled up or pulled down. This pin can ramp up before VDD. |
8 | SDA/SCLK | Input/Output | Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external pullup resistor in I2C mode. This pin can ramp up before VDD. |
9 | NC | NC | No connection. Leave the pin unconnected. |
10 | NC | NC | No connection. Leave the pin unconnected. |
11 | OUT1 | Output | Analog output voltage from DAC channel 1. |
12 | FB1 | Input | Voltage
feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current. |
13 | CAP | Power | External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND. |
14 | AGND | Ground | Ground reference point for all circuitry on the device. |
15 | VDD | Power | Supply voltage. |
16 | VREF | Power | External
reference input. Connect a capacitor (approximately 0.1 μF) between
VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case an external reference is used, make sure the reference ramps up after VDD. |
Thermal pad | Thermal Pad | Ground | Connect the thermal pad to AGND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage, VDD to AGND | –0.3 | 6 | V |
Digital inputs to AGND | –0.3 | VDD + 0.3 | V | |
CAP to AGND | –0.3 | 1.65 | V | |
VFBX to AGND | –0.3 | VDD + 0.3 | V | |
VOUTX to AGND | –0.3 | VDD + 0.3 | V | |
VREF | External reference, VREF to AGND | –0.3 | VDD + 0.3 | V |
Current into any pin except the OUTx pins | –10 | 10 | mA | |
TJ | Junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±500 |