DAC8550 16-bit, Ultra-Low Glitch, Voltage Output Digital-To-Analog Converter
1 Features
- Relative Accuracy: 8 LSB
- Glitch Energy: 0.1 nV-s
- MicroPower Operation: 140 μA at 2.7 V
- Power-On Reset to Midscale
- Power Supply: 2.7 V to 5.5 V
- 16-Bit Monotonic
- Settling Time: 10 μs to ±0.003% FSR
- Low-Power Serial Interface with Schmitt-Triggered Inputs
- On-Chip Output Buffer Amplifier with Rail-to-Rail Output Amplifier
- Power-Down Capability
- 2's Complement Input
- SYNC Interrupt Facility
- Drop-In Compatible with DAC8531/01 and DAC8551 (Binary Input)
- Available in a Tiny MSOP-8 Package
2 Applications
- Process Control
- Data Acquisition Systems
- Closed-Loop Servo-Control
- PC Peripherals
- Portable Instrumentation
- Programmable Attenuation
3 Description
The DAC8550 is a small, low-power, voltage output, 16-bit digital-to-analog converter (DAC). It is monotonic, provides good linearity, and minimizes undesired code-to-code transient voltages. The DAC8550 uses a versatile, 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI™, QSPI™, Microwire™, and digital signal processor (DSP) interfaces.
The DAC8550 requires an external reference voltage to set its output range. The DAC8550 incorporates a power-on reset circuit that ensures that the DAC output powers up at midscale and remains there until a valid write takes place to the device. The DAC8550 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200 nA at 5 V.
The low-power consumption of this device in normal operation makes it ideal for portable, battery-operated equipment. Power consumption is 0.38 mW at 2.7 V, reducing to less than 1 μW in power-down mode.
The DAC8550 is available in an MSOP-8 package.
For additional flexibilty, see the DAC8551, a binary-coded counterpart to the DAC8550.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| DAC8550 | VSSOP (8) | 3.00 mm × 3.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Functional Block Diagram
4 Revision History
Changes from G Revision (February 2017) to H Revision
- Changed the VIL Test Conditions From: VDD = 5 V To: 3 V ≤ VDD ≤ 5.5 V and From: VDD = 3 V To: 2.7 V ≤ VDD < 3 V in the Electrical CharacteristicsGo
- Changed the VIH Test Conditions From: VDD = 5 V To: 3 V ≤ VDD ≤ 5.5 V and From: VDD = 3 V To: 2.7 V ≤ VDD < 3 V in the Electrical CharacteristicsGo
Changes from F Revision (March 2016) to G Revision
- Relative accuracy DAC8550, Deleted the TYP value of ± 3, Changed the MAX value From: ±8 To: ±16 in the Electrical Characteristics Go
- Relative accuracy DAC8550B, Deleted the TYP value of ± 3, Changed the MAX value From: ±8 To: ±12 in the Electrical Characteristics Go
Changes from E Revision (March 2012) to F Revision
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
- Changed Differential nonlinearity Test Conditions From: 16-bit monotonic To: three separate entries in the Electrical Characteristics Go
Changes from D Revision (October 2006) to E Revision
- Changed low-level input voltage values in Electrcial CharacteristicsGo
- Changed high-level input voltage values in Electrcial CharacteristicsGo
Changes from C Revision (March 2006) to D Revision
- Changed FeaturesGo
- Changed relative accuracy feature from 8 LSB (Max) to 3 LSBGo
- Changed micropower operation feature from 200 μA at 5 V to 140 μA at 2.7 VGo
- Changed power consumption from 1 mW at 5 V to 0.38 mW at 2.7 VGo
- Changed power-down consumption from 1 mW to less than 1 mW in DescriptionGo
- Changed relative accuracy for DAC8550 typical value from ±5 to ±3Go
- Changed reference current input range for VREF = 5 V from 50 to 40Go
- Deleted reference current included from IDD (normal mode) test conditionsGo
- Changed IDD (normal mode) typical values from 200 and 180 to 160 and 140Go
- Changed Timing Diagram and Timing CharacteristicsGo
5 Pin Configuration and Functions
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| VDD | 1 | PWR | Power-supply input |
| VREF | 2 | I | Reference voltage input |
| VFB | 3 | I | Feedback connection for the output amplifier |
| VOUT | 4 | O | Analog output voltage from DAC. The output amplifier has rail-to-rail operation. |
| SYNC | 5 | I | Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8550). Schmitt-Trigger logic input. |
| SCLK | 6 | I | Serial clock input. Data can be transferred at rates up to 30 MHz Schmitt-Trigger logic input. |
| DIN | 7 | I | Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input. |
| GND | 8 | GND | Ground reference point for all circuitry on the part |