The DRV8836 provides an integrated motor driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered motion control applications. The device has two H-bridge drivers, and can drive two DC motors or one stepper motor, as well as other devices like solenoids. The output driver block for each consists of N-channel power MOSFET configured as an H-bridge to drive the motor winding. An internal charge pump generates gate drive voltages.
The DRV8836 supplies up to 1.5-A of output current per H-bridge. It operates on a power supply voltage from 2 V to 7 V.
PHASE/ENABLE and IN/IN interfaces can be selected which are compatible with industry-standard devices. A low-power sleep mode is provided which turns off all unnecessary logic to provide a very low current state.
Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature.
The DRV8836 is packaged in a tiny 12-pin WSON package (Eco-friendly: RoHS and no Sb/Br).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8836 | WSON (12) | 2.00 mm x 3.00 mm |
Changes from C Revision (December 2015) to D Revision
Changes from B Revision (January 2014) to C Revision
Changes from A Revision (September 2013) to B Revision
PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
|
---|---|---|---|---|
NAME | NO. | |||
POWER AND GROUND | ||||
GND, Thermal pad | 6 | — | Device ground | |
VCC | 1 | — | Device and motor supply | Bypass to GND with a 0.1-μF (minimum) ceramic capacitor |
CONTROL | ||||
AIN1/APHASE | 10 | I | Bridge A input 1/PHASE input | IN/IN mode: Logic high sets AOUT1 high PH/EN mode: Sets direction of H-bridge A Internal pulldown resistor |
AIN2/AENBL | 9 | I | Bridge A input 2/ENABLE input | IN/IN mode: Logic high sets AOUT2 high PH/EN mode: Logic high enables H-bridge A Internal pulldown resistor |
BIN1/BPHASE | 8 | I | Bridge B input 1/PHASE input | IN/IN mode: Logic high sets BOUT1 high PH/EN mode: Sets direction of H-bridge B Internal pulldown resistor |
BIN2/BENBL | 7 | I | Bridge B input 2/ENABLE input | IN/IN mode: Logic high sets BOUT2 high PH/EN mode: Logic high enables H-bridge B Internal pulldown resistor |
MODE | 11 | I | Input mode select | Logic low selects IN/IN mode Logic high selects PH/EN mode Internal pulldown resistor |
nSLEEP | 12 | I | Sleep input | Active low places part in low-power sleep state Internal pulldown resistor |
OUTPUT | ||||
AOUT1 | 2 | O | Bridge A output 1 | Connect to motor winding A |
AOUT2 | 3 | O | Bridge A output 2 | |
BOUT1 | 4 | O | Bridge B output 1 | Connect to motor winding B |
BOUT2 | 5 | O | Bridge B output 2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Power supply voltage, VCC | –0.3 | 7 | V | ||
Digital input pin voltage | –0.5 | VCC + 0.5 | V | ||
Peak motor drive output current | Internally limited | A | |||
Continuous motor drive output current per H-bridge(3) | –1.5 | 1.5 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Device power supply voltage | 2 | 7 | V |
VIN | Logic level input voltage | 0 | VCC | V |
IOUT | H-bridge output current(1) | 0 | 1.5 | A |
fPWM | Externally applied PWM frequency | 0 | 250 | kHz |
THERMAL METRIC(1) | DRV8836 | UNIT | |
---|---|---|---|
DSS (WSON) | |||
12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 50.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 58 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 20 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.9 | °C/W |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | t1 | Delay time, xPHASE high to xOUT1 low | 210 | ns | |
2 | t2 | Delay time, xPHASE high to xOUT2 high | 150 | ns | |
3 | t3 | Delay time, xPHASE low to xOUT1 high | 150 | ns | |
4 | t4 | Delay time, xPHASE low to xOUT2 low | 210 | ns | |
5 | t5 | Delay time, xENBL high to xOUTx high | 150 | ns | |
6 | t6 | Delay time, xENBL high to xOUTx low | 150 | ns | |
7 | t7 | Output enable time | 210 | ns | |
8 | t8 | Output disable time | 210 | ns | |
9 | t9 | Delay time, xINx high to xOUTx high | 125 | ns | |
10 | t10 | Delay time, xINx low to xOUTx low | 125 | ns | |
11 | tR | Output rise time | 20 | 188 | ns |
12 | tF | Output fall time | 8 | 30 | ns |
The DRV8836 is an integrated motor driver solution used for brushed motor control. The device integrates two
H-bridges, and can drive two DC motor or one stepper motor. The output driver block for each H-bridge consists of N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature protection.
The bridges connect in parallel for additional current capability.
The mode pin allows selection of either a PHASE/ENABLE or IN/IN interface.
If the nSLEEP pin enters a logic-low state, the DRV8836 enters a low-power sleep mode. In this state all unnecessary internal circuitry is powered down.
There is a weak pulldown resistor (approximately 100 kΩ) to ground on the input pins.
The DRV8836 is fully protected against undervoltage, overcurrent, and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disable. After approximately
1 ms, the bridge re-enables automatically.
Overcurrent conditions on both high and low side devices, like a short to ground, supply, or across the motor winding results in an overcurrent shutdown.
If the die temperature exceeds safe limits, all FETs in the H-bridge disable. Once the die temperature has fallen to a safe level operation automatically resumes.
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device disables, and internal logic resets. Operation resumes when VCC rises above the UVLO threshold.
FAULT | CONDITION | ERROR REPORT | H-BRIDGE | INTERNAL CIRCUITS | RECOVERY |
---|---|---|---|---|---|
VCC undervoltage (UVLO) | VCC < VUVLO | None | Disabled | Disabled | VCC > VUVLO |
Overcurrent (OCP) | IOUT > IOCP | None | Disabled | Operating | tOCR |
Thermal shutdown (TSD) | TJ > TTSD | None | Disabled | Operating | TJ < TTSD – THYS |
The DRV8836 is active when the nSLEEP pin is set to a logic high. When in sleep mode, the H-bridge FETs disable (Hi-Z).
OPERATING MODE | CONDITION | H-BRIDGE | INTERNAL CIRCUITS |
---|---|---|---|
Operating | nSLEEP high | Operating | Operating |
Sleep mode | nSLEEP low | Disabled | Disabled |
Fault encountered | Any fault condition met | Disabled | See Table 1 |
Two control modes are available in the DRV8836: IN/IN mode and PHASE/ENABLE mode. IN/IN mode is selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is driven to logic high. The following tables show the logic for these modes.
MODE | xIN1 | xIN2 | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
---|---|---|---|---|---|
0 | 0 | 0 | Z | Z | Coast |
0 | 0 | 1 | L | H | Reverse |
0 | 1 | 0 | H | L | Forward |
0 | 1 | 1 | L | L | Brake |
MODE | xENABLE | xPHASE | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
---|---|---|---|---|---|
1 | 0 | X | L | L | Brake |
1 | 1 | 1 | L | H | Reverse |
1 | 1 | 0 | H | L | Forward |
NOTE
The information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DRV8836 is used in one or two motor control applications. When configured in parallel, the DRV8836 provides double the current to one motor.
The two H-bridges in the DRV8836 can be connected in parallel for double the current of a single H-bridge. Figure 5 shows the connections.
The following design is a common application of the DRV8836.
The design requirements are shown in Table 5.
DESIGN PARAMETER | REFERENCE | EXAMPLE VALUE |
---|---|---|
Motor voltage | VCC | 4 V |
Motor RMS current | IRMS | 0.3 A |
Motor startup current | ISTART | 0.6 A |
Motor current trip point | ILIMIT | 0.5 A |
The following design procedure can be used to configure the DRV8836 in a brushed motor application.
The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings.
When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power.
The following scope captures motor startup as VCC ramps from 0 V to 6 V. Channel 1 is VCC, and Channel 4 is the motor current of an unloaded motor during startup. The motor used is a NMB Technologies Corporation OOB7PA12C, PPN7PA12C1. As VCC ramps the current in the motor increases until the motor speed builds up. The motor current then reduces for normal operation.
Inputs are set as follows:
The appropriate local bulk capacitance is an important factor in motor drive system design. More bulk capacitance is generally beneficial but may increase costs and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
The inductance between the power supply and motor drive system limits the rate current changes from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.
The datasheet provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor.
The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1-μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace or ground plane connection to the device GND pin.
The VCC pin must bypass to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8836.
The DRV8836 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or an ambient temperature that is too high.
The power dissipated in the output FET resistance or RDS(on) dominates the power dissipation in the DRV8836. The average power dissipation when running both H-bridges can be roughly estimated by Equation 1:
where
The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking.
NOTE
RDS(ON) increases with temperature. As the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink.
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.
For more information on PCB design, refer to TI application report SLMA002, PowerPAD™ Thermally Enhanced Package, and TI application brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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