The OPA593 is a high-voltage, high-output-current power amplifier (PA) that operates on an 85V single supply or a ±42.5V dual-supply configuration, with the capability to source or sink current up to ±250mA. This article focuses on dual-supply rail configurations, favored for their programmable and flexible precision voltage regulator setups commonly used in automated test equipment (ATE) applications. While the OPA593 meets the output voltage requirements for most power voltage regulator applications, OPA593 does not provide sufficient current drive in certain scenarios. In such cases, combining the OPA593 with a current booster topology can enhance the current drive capabilities while maintaining the amplifier’s overall operating voltage range, bandwidth, accuracy, and responsiveness to timing requirements.

In practice, a large capacitive load is often connected to the output of a power amplifier stage. Capacitive loads serve several purposes, including decoupling, filtering high-frequency noise, reducing voltage spikes, stabilizing transient responses, and improving output voltage regulation at the device under test (DUT). However, adding capacitive loads can introduce undesirable phase lag, potentially leading to loop instability in the power amplifier's feedback system.

Driving large capacitive loads presents significant design challenges for engineers, particularly in compensating for stability issues. This application note addresses these challenges when using the OPA593 with a Darlington current booster configuration. The document also explores the trade-offs associated with this technique, especially when driving capacitive loads up to 1µF.

Figure 1-1 and Table 2-2 present the schematic discussed in this application note, which aims to meet (or exceed) the design requirements.

Figure 1-1 The OPA593 With a Current Booster Circuit Drives 1μF Capacitive Load, C_L

The current booster’s open-loop output impedance and frequency response are among the key parameters in selecting a driver for ATE applications. The following criteria are summarized.

Line items 1 through 3 in Table 2-2 regarding the current booster are addressed in Sections 2 and 3 of the article.

In this design, the current booster is configured as a complementary push-pull Darlington topology with unity gain buffering. Figure 2-1 and Figure 2-2 demonstrate that the open-loop output impedance is regulated by a small bias voltage applied to the bases of the transistors. Forward biasing the base-emitter junction of the NPN transistor (T1) allows the booster to source positive voltage and current, while forward biasing the PNP transistor (T2) enables it to sink negative voltage and current. The bias voltage directly affects the open-loop output impedance; higher bias levels result in lower output impedance, as shown in Equation 1.

Where,

• r_o represents the BJT’s output impedance
• V_A refers to the Early voltage
• I_C denotes the bipolar collector current
• r_op represents the NPN’s open-loop output impedance
• r_on represents the PNP’s open-loop output impedance
• Z_CE represents the parallel output impedance of the complementary Darlington pair
• Z_CBO refers to the overall parallel open-loop output impedance

When the NPN transistor (T1) base-emitter junction is forward-biased, the current booster sources positive voltage and current at the output. Figure 2-1 illustrates the open-loop output impedance where the effects of Z_CE ∥R_L are shown to be less than 1Ω.

Conversely, when the emitter-base junction of the PNP transistor (T2) is forward-biased, the current booster sinks negative voltage and current at the output. Figure 2-2 demonstrates the open-loop output impedance, with the Z_CE ∥R_L effects yielding similar results. The combined open-loop output impedance remains consistent across the frequency range up to 1MHz.

Figure 2-1 Open-Loop Output Impedance (Z_CBO) with T1 Forward Biased

Figure 2-2 Open-Loop Output Impedance (Z_CBO) with T2 Forward Biased

The BJT transistor's forward biased voltage directly affects the open-loop output impedance; higher bias voltages lead to lower output impedance. The open-loop output impedance of the push-pull complementary BJT driver is primarily influenced by the output resistances (r_o) of the NPN (r_op) and PNP (r_on) transistors, as well as the load resistance (R_L). The open-loop output impedance of the Darlington current booster operates in parallel with R_L, as illustrated in Equation 1.

A simplified current booster without a preconfigured forward bias can be adequate for voltage regulators with discrete setpoints; however, a simplified current booster is not designed for applications that require minimal non-linearity and distortion. In a Darlington configuration, a dead zone of approximately 1.3V occurs when the transistors do not receive sufficient biased voltage, resulting in a lack of output current amplification and exhibiting a cutoff characteristic. This situation can delay the step response, as the booster must first overcome the V_BE threshold. Adding a zero-crossover resistor, R_ZRO (for example, 1-10kΩ), can alleviate this dead zone, as shown in Figure 2-3, allowing some output current to flow even when the transistors are non-conductive. This modification does not affect the open-loop output impedance, as shown in Figure 2-4.

Figure 2-3 Minimize Crossover Distortion with Zero-Crossover Resistor (R_ZCO)

By placing a 10kΩ zero-crossover resistor (R_ZRO) inside the common emitter current booster, as shown in Figure 2-4, the open-loop output impedance of the current booster driver remains unaffected.

Figure 2-4 Open-Loop Output Impedance Remains Unaffected by R_ZCO

Various current booster pairs are designed for this application, with "C" indicating complementary pairs in which power transistors must be matched for ATE applications. Options include discrete CMOSFET, CBJT, or CIGBT, as well as integrated open-loop buffers (for example, BUF634A, LME49600) and power amplifiers utilized as unity gain buffers (for example, OPA593, OPA544). Table 3-1 compares the advantages and disadvantages of CMOSFET and CBJT current boosters, emphasizing key trade-offs and differences. Choosing the correct current booster requires understanding these variations and the implications for performance and cost.

Table 3-1 compares the pros and cons of CMOSFET and CBJT current drivers, which are two of the most popular and cost-effective options. Although detailed comparisons are not provided in this section, note that there are significant differences and trade-offs that need to be considered when selecting current boosters for a specific application.

To effectively understand dual feedback compensation (DFC) techniques and make sure of loop stability, recognize the interactions between resistive and capacitive loads, as well as the open-loop output impedance of the power amplifier. Proper management of the placement of poles and zeros within a feedback system is vital for achieving stability and performance.

Using a power amplifier (PA) Spice model, such as the one provided by the Tina simulator, can streamline the analysis and enhance comprehension of the DFC approach. This model mimics the performance characteristics of the OPA593 with the current booster composite amplifier, offering a clear framework for understanding the DFC technique. The emulated Spice model emphasizes the key interactions among compensated components, including the output resistive load (R_L), capacitive load (C_L), feedback resistors (R_F, R_I), and the op-amp's open-loop output impedance (Z_o), as shown in Figure 4-1.

Table 4-1summarizes the op-amp behaviors of the emulated Spice model for the OPA593 + current booster composite amplifier. Table 4-2 outlines the design requirements for the power amplifier, which is intended to drive 1μF capacitive and resistive loads with an output current rated up to ±1A_dc.

Figure 4-1 Emulated Power Amp Drives a Resistive Load - Open-Loop AC Stability Analysis

In the simulator, an ideal power amplifier is modified to demonstrate the DFC compensation technique. Table 4-1 summarizes the key parameters of this modified power amplifier (PA). The simulation results in Figure 4-1 validate the model's behavior and confirm its consistency with the SPICE model. The unity gain bandwidth calculated from the gain bandwidth product (GBP) is approximately 1.2MHz, while the phase margin is approximately 88.6°.

In automated test equipment (ATE) applications, the output stage of a power amplifier frequently interfaces with substantial capacitive loads. Driving large capacitive loads (for example, 1μF) presents challenges due to an additional pole introduced within the op-amp’s unity-gain bandwidth (UGBW). This extra pole (f_p2), described in Equation 4 can destabilize the op-amp’s loop gain and reduce the phase margin in the closed loop within the UGBW.

No op-amp can drive large capacitive loads while making sure of stability without appropriate feedback loop compensation. The term "large capacitive load" is relative and varies based on several factors, including the op-amp's open-loop output impedance, load resistance, load capacitance, and unity-gain bandwidth (f_unity). Typically, op-amps can drive capacitive loads ranging from 10pF to 100pF without requiring external compensation. Op-amps with low open-loop output impedance can drive higher capacitive loads, up to 1nF, while still maintaining adequate phase margin without additional compensation. However, capacitive loads exceeding 1nF are generally considered "large" and can lead to issues such as oscillation, making compensation essential for preserving loop stability.

While some op-amps can drive capacitive loads up to 1nF, others can become unstable. This distinction depends on the op-amp’s open-loop output impedance, the interaction with the capacitive load (C_L), and the location of the extra pole (f_p2 ) relative to unity-gain bandwidth (UGBW). These factors collectively determine an op-amp's ability to drive capacitive loads effectively. Table 4-4 summarizes the stability of an op-amp when driving capacitive loads under various scenarios.

In summary, the stability of an op-amp driving capacitive loads is influenced by the relationship between the second pole (f_p2) and the UGBW. If f_p2 is far beyond the UGBW, the system remains stable. However, if f_p2 is within or near the UGBW, the op-amp can become unstable or conditionally stable.

The phase margin, obtained from open-loop AC analysis, is a quantitative measure to evaluate the stability of an op-amp in a closed-loop feedback configuration. Phase margin predicts whether the system can remain stable, oscillate, or exhibit uncertain behavior, especially when driving capacitive loads. A phase margin of at least 45° is generally required to make sure of stable operation according to open-loop AC stability analysis.

How to adequately compensate capacitive loads in op-amps is well documented in the Precision Lab Series: Op Amps. This video series provides an overview of theories, simulations, examples and application notes.

One technique covered is the Dual Feedback Compensation (DFC) method, commonly used to compensate for complex loads in op-amps. However, detailed information on this technique is limited, particularly concerning current booster configurations like the OPA593 combined with a current booster driver.

The DFC technique mitigates the effects of capacitive loads, as demonstrated in Figure 4-2. This method involves placing an isolation resistor in series with the op-amp’s output or within the feedback path. The combination of the op-amp’s output impedance (Z_o + R_iso​) with the capacitive load (​C_L) introduces an additional pole (f_p2​), derived from Equation 4.

To estimate R_iso​, use the provided equation and select the nearest standard resistor value. In this example, the gain bandwidth product is defined at 10MHz, with a gain of 8V/V. The op-amp's closed-loop dominant pole (f_dom, 10MHz/8) is calculated to be 1.25MHz. The emulated op-amp’s open-loop output impedance, Z_o, is modeled at 1Ω across all frequencies, and R_iso is determined to be 356.8mΩ, approximately 357mΩ, as calculated from Equation 3.

The open-loop AC loop analysis focuses on determining the UGBW, loop gain, phase margins and other small signal stability parameters, as shown in Figure 4-2. Next, the compensated op-amp configuration is simulated to verify the circuit's closed-loop stability. This verification is achieved by applying a small step transient signal at the op-amp input during closed-loop operation. Making sure of the stability of an op-amp driving a complex load requires at least two simulation steps. The loop-stability iteration process optimizes the compensation between open-loop AC characteristics and closed-loop feedback responses. Without the proper step sequence, the op-amp's closed-loop behavior is undetermined, and output oscillatory behavior can manifest, as the uncompensated op-amp demonstrated in Figure 4-3.

Figure 4-2 Open-Loop AC Analysis of an Uncompensated Op-amp With R_iso

When an op-amp feedback system drives a capacitive load, understanding the interaction between the open-loop output impedance and the load capacitance is crucial. The emulated power amplifier’s open-loop output impedance, Z_o, is defined at 1Ω across all frequencies.

When driving 1μF capacitive load, a newly generated pole is calculated to be approximately 118kHz, as presented in Equation 4. Without the capacitive load, the unity gain bandwidth, f_unity, was simulated at 1.25MHz with a phase margin of 88.6°, as shown in Figure 4-1. Introducing the capacitive load causes f_unity to decrease, reducing the op-amp's roll-off slope from -20dB/decade to -40dB/decade, and the UGBW from 1.25MHz to approximately 374kHz. This additional pole reduces the phase margin from 88.6° to 17.4°, limiting the overall bandwidth of the system.

Figure 4-3 Uncompensated Op-Amp Driving 1μF Load - Unstable

To stabilize the feedback loop in Figure 4-2, set the additional f_p2 pole frequency approximately 1 to 2 octaves lower than the simulated 374kHz. With the effective bandwidth defined at 50kHz in Table 4-2, we assign this value to f_{DFC_BW} and calculate C_F using Equation 5, estimating the result to be approximately 455pF. A standard capacitor value of 420pF is selected, as shown in Figure 4-4.

Figure 4-4 Outer Feedback Loop Compensation Bode Plot Driving (Z_o + R_iso )∥R_L and C_L

The effective bandwidth of the DFC technique refers to the frequency range in which the op-amp achieves the desired gains and performance. In a dual feedback compensation topology, the op-amp bandwidth is not determined by the gain bandwidth product (GBP); instead, the effective bandwidth is primarily influenced by external compensation components, such as R_iso, R_F and C_F, as illustrated in Figure 4-5 and described in Equation 5. The compensation of the outer pole in the feedback loop, represented as approximately 1/sR_FC_F, defines the effective bandwidth (f_{DFC_BW}) of the DFC configuration.

Figure 4-5 DFC Overall Open-Loop AC Analysis: 2.6MHz UGBW and Phase Margin 89°

The small-signal step transient simulation plot confirms that the DFC is stable in the closed loop, as shown in Figure 4-6. There is no output overshoot, and the design meets the timing requirements outlined in Table 4-2.

Figure 4-6 The Compensated Closed-Loop Response: Step Transient Analysis in Driving 1μF Load

The final validation step in the simulation involves a frequency sweep of the OPA593 with the current booster and analyzing the gain responses, as shown in Figure 4-7. If the AC gains increase with frequency near the -3dB point, it typically suggests that two poles are too closely spaced or overlapped. This phenomenon is discussed in the next section.

Figure 4-7 AC Frequency Sweep of the Emulated PA Driving 1μF Load

The DFC technique for compensating capacitive loads is complex. One challenge in optimizing DFC is that the effective bandwidth often exhibits gain peaking or Q effects in the AC frequency response. Gain peaking or a high Q factor indicates that more than one pole is present within the UGBW, a phenomenon characteristic of the DFC method, as illustrated in Figure 4-8. Gain peaking occurs when poles are closely spaced or overlapped within the closed feedback loop, resulting in resonant responses that elevate gains. This effect is observable only when the feedback loop is closed, whether in the time or frequency domain.

In the op-amp compensated for 1µF capacitive load, as depicted in Figure 4-8, the resistance R_iso values are progressively increased from 100mΩ, 500mΩ, 1Ω, and 5Ω. The selection of R_iso​ is relative to the op-amp’s open-loop output impedance, defined at 1Ω across all frequencies in the emulated Spice model. As R_iso increases, the additional pole f_p2 shifts toward lower frequencies, as described by Equation 4. This pole shift contributes to gain peaking in the frequency response when the newly emerged pole moves closer to the dominant pole, f_{DFC_BW}​ defined in the DFC loop. Gain peaking occurs when these two poles overlap or come too close together, as shown in Figure 4-8.

To optimize the value of R_iso in the DFC technique and eliminate guesswork, Equation 3 is used to calculate R_iso, based on the following Determine Optimal Isolation Resistance for Driving Capacitive Load, application note. The R_iso value must be significantly lower than both Zo and R_F​ parameters. A larger R_iso value can adversely affect the gain peaking or quality factor (Q) of the compensation loop, potentially altering the circuit's stability and effective bandwidth.

Figure 4-8 Effect of R_iso of the Compensated Op-Amp Driving 1μF Capacitive Load

The DFC technique utilizes two distinct feedback paths to improve overall loop stability: a low-frequency feedback path and a high-frequency feedback path, as shown in Figure 1-1. The low-frequency feedback path serves as the outer feedback loop, establishing nominal gains and bandwidth based on the op-amp’s dominant pole, defined by f_{DFC_BW} in Equation 5.

Conversely, the high-frequency feedback path serves as the inner feedback loop, operating at a higher bandwidth than the outer loop. These dual feedback loops interact, where the UGBW of the inner feedback loop resembles a pole in relation to the UGBW of the outer loop. This interaction affects both bandwidth and phase levels, impacting the overall stability of the system.

The DFC procedures are summarized in Table 4-4, along with some of the simulated parameters used in the article.

• The feedback resistor R_F is chosen based on the requirement of ±40V_dc and ±10mA, resulting in a minimum resistance of 4kΩ, as 10mA is the input current at the OPA593’s absolute maximum rating. For simulation, a 7kΩ resistor was used. However, in real-world ATE applications, an R_F value closer to 14kΩ is recommended to make sure of additional limiting current within the design margin.
• In the OPA593, asymmetric power supply rails of +43V_dc and -42V_dc are used. During simulation, the output voltage swing was ±2V below the supply rails. In practical applications, ±42.5V_dc needs to suffice to achieve an output of ±40.0V_dc. To reduce heat dissipation, it is crucial to minimize the voltage difference between the supply rails and the output.

The design approach using the OPA593 with a Darlington current booster topology for driving 1µF capacitive load follows the dual feedback compensation (DFC) process designed for the emulated power amplifier, shown in Figure 4-5. A key difference is that the current booster effectively acts as the isolation resistor (R_iso) in the designed emulated PA example. While the OPA593 maintains an output impedance of approximately 228Ω from 1kHz to 1MHz, this is not designed for driving large capacitive loads using the compensation technique outlined in Table 4-4, where alternative DFC compensation techniques are more appropriate.

The design requirements for the OPA593 and the current booster configuration are detailed in Table 2-2 at the beginning of the article. Integrating the OPA593 with a Darlington current booster creates a composite amplifier with low open-loop output impedance. This composite amplifier benefits from the OPA593’s performance attributes—such as high input voltage handling, high slew rate, current limiting, and Enable or Disable functionality. These features make the OPA593 capable of driving large capacitive loads and meeting high current demands in ATE applications, provided that the feedback network is properly compensated.

In the current booster configuration shown in Figure 5-1, simulations reveal that the unity gain bandwidth, f_unity of the OPA593 combined with the Darlington current booster remains consistent, with a measured f_unity of approximately 1.4MHz and a phase margin of 79°. When the gain bandwidth product is applied, the simulation results closely match those of the emulated power amplifier depicted in Figure 4-1. This suggests that the closed-loop of the composite amplifier needs to exhibit similar behaviors as the emulated power amplifier.

Figure 5-1 OPA593 + Current Booster Driving Resistive Load with V_REF = 1V_dc

When a capacitive load of C_L = 1μF is introduced at the output of the current booster stage, a second pole, f_p2, is estimated to occur at approximately 320kHz, as determined by Equation 4. This pole falls within the UGBW, measured at 549kHz, resulting in significant phase lag and reducing the phase margin from 79° to –19.4°, as illustrated in Figure 5-2. Consequently, the combination of the OPA593 and the current booster becomes unstable when driving 1μF capacitive load in the closed-loop configuration.

Figure 5-2 OPA593 + Current Booster's Outer Feedback Loop AC Analysis - Driving 1μF (C_L)∥100Ω (R_L)

To stabilize the outer feedback loop, it is crucial to account for the additional pole, f_p2, at approximately 320kHz, arising from the interaction between Z_CBO (~0.5Ω) and C_L. A common technique in DFC is to reduce the outer loop-gain by incorporating a compensation capacitor, C_F. This capacitor ensures that the outer loop's UGBW is at least 1-2 octaves below f_p2. A conservative guideline recommends setting the outer loop's UGBW two octaves below f_p2, translating to less than 100kHz, to maintain stability within the multiple feedback loop compensation scheme. While larger values of C_F can improve overall DFC stability, they also significantly limit the circuit’s effective bandwidth, creating a trade-off that designers must carefully evaluate based on application requirements. Other DFC methods, primarily involving pole-zero cancellation, can also effectively address the pole that appears at the outer feedback loop's UGBW. However, detailed compensation procedures are beyond the scope of this application note.

According to the design requirements outlined in Table 2-2 and Equation 5, the target cutoff frequency, f_{DFC_CB_BW}, is defined at approximately 50kHz. To achieve this specification, the compensation capacitor, C_F is calculated to be around 455pF. The closest standard value, C_F ≈ 420pF, is then chosen. As shown in Figure 5-3, the simulated outer feedback loop’s UGBW is measured at 50.8kHz, with a phase margin of approximately 76°, based on the open-loop AC analysis. Consequently, the outer feedback loop is expected to remain stable during closed-loop operation, as indicated by the perturbation injection analysis.

Figure 5-3 OPA593 + Current Booster Composite Amplifier's Outer Feedback Loop Stability

As mentioned in the Summary of Section 4, the DFC technique utilizes dual feedback loop compensation. In Figure 5-3, we examined the AC stability of the outer feedback loop. Now, we can analyze the inner feedback loop, which is responsible for high-frequency compensation. This inner loop is crucial for determining overall AC loop stability, and can be simplified as the Loop-Gain of the DFC technique. Figure 5-3 shows the AC loop gain stability analysis, and the compensation approach is detailed in the Precision Lab Series: Op Amp.

Figure 5-4 Open-loop AC Analysis in DFC shows a Phase Margin of 58° at the UGBW

From the AC stability analysis in Figure 5-4, the unity gain bandwidth of the loop gain is measured at 5.46MHz with a phase margin of approximately 58°, indicating that the overall DFC loop is stable.

To assess the closed-loop behavior of the compensated OPA593 in the current booster configuration, a small signal step transient analysis was performed, as shown in Figure 5-5. The closed-loop transient response reveals no overshoot or oscillation, indicating a sufficient phase margin and effective compensation applied to the inner and outer feedback loops.

Figure 5-5 Compensated Composite Amplifier - Step Transient Response in Time Domain

Like the emulated power amplifier in Section 4, gain peaking or Q effects can be more pronounced in actual op-amp simulations. Each op-amp design contains numerous hidden poles and zeros. While these high frequency poles and zeros typically do not interfere with single feedback loop compensation within the UGBW, the DFC compensation methods can be an exception, particularly when managing multiple feedback loops. Thus, it is crucial to examine the AC frequency response behavior, to verify sweep frequency response in ATE applications, as shown in Figure 5-6.

Figure 5-6 OPA593 and Current Booster's Effective Bandwidth: AC Sweep in Frequency Domain

Note the importance to clarify the concepts of op-amp bandwidth and step timing response in ATE applications, as engineers often confuse these terms.

An op-amp's effective bandwidth is derived from AC small-signal analysis in a linear model, which describes how quickly the amplifier can respond to small-signal changes at both the input and output while maintaining a relatively constant gain. This model defines the frequency range in which the amplifier can perform effectively in a specific closed-loop configuration. In a closed-loop feedback system, the op-amp bandwidth is a first-order approximation based on the gain-bandwidth product.

In contrast, an op-amp's step response or timing requirements are associated with the slew rate and the characteristics of the input signal, which are typically evaluated using the large-signal model. For ATE applications, step timing responses are generally very rapid, typically on the order of 10µs from applying the input signal to stabilizing the output setpoint, which are critical design parameters.

When output stages are loaded with capacitive or inductive components, longer time constants are introduced due to these load parameters. Merely increasing the op-amp bandwidth does not resolve the time delay or significantly enhance the step response.

To improve the step response time in ATE applications, output driving stages must provide a higher current rate over a short duration. For larger capacitive loads, achieving a fast output voltage setpoint requires rapid feedback control and a high rate of current change to drive the capacitive load, represented as C(di/dt). In the OPA593 + current booster configuration, the large signal step response time is determined by the slew rate of the OPA593 and the rate of current change in the booster driver (for example, di/dt). Overall performance is also influenced by the compensated op-amp, output voltage swing, settling time, and transient overshoot or undershoot behaviors. Thus, a trade-off must be made between minimizing output current spikes and optimizing step response time in ATE applications.

To validate the OPA593 and Darlington current booster DFC configuration, the OPA593 Evaluation Module (OPA593EVM) was modified to include the Darlington current booster output stage, replicating the circuit simulated in the Spice model shown in Figure 1-1. The circuit validations and improvements are summarized as follows:

1. The small-signal step transient response is stable with no overshoot or oscillation.
2. Both large-signal and small-signal step transient behaviors meet the design criteria.
3. The effective bandwidth of the current booster is measured at approximately 60kHz as specified.
4. Rise and fall times in signal step responses are within the specified design parameters.
5. Voltage accuracy requirements are met, and the circuit can source and sink current up to ±1A_dc.
6. The OPA593 and the current booster composite amplifier remain stable when driving a capacitive load up to 1µF.
7. Improvement: Enhanced heat dissipation for the Darlington booster transistors.
8. Improvement: Incorporation of short-circuit protection through programmable current-limiting features.
9. Improvement: Implementation of Enable/Disable control for shutdown and fault condition management.

The combination of the OPA593 and the current booster demonstrates that the small signal step transient is stable while driving 1µF capacitive load in parallel with a 52.5Ω resistive load. The small signal and larger signal step transient scope shots are captured and presented in Figure 7-1 and Figure 7-2.

Figure 7-1 The OPA593 Composite Amplifier in Small Signal Step Response: Driving 1μF C_L Load

Figure 7-2 OPA593 and Current Booster in Larger Signal Step Response: Driving 1μF C_L Load

In terms of current booster improvements, the specific application received less attention since the application note primarily focused on stability compensation for the composite amplifier using the OPA593 or similar op-amps. However, a few essential design considerations were noted. The OPA593 has built-in current limiting and enable/disable protection features. By leveraging these features, the thermal and fault protection circuits of the composite power amplifier can be simplified, providing adequate protection for the CBJT while reducing reliance on additional protective components.

This article explores the OPA593 in a current booster topology, using the DFC compensation technique to stabilize large capacitive loads in a voltage regulator configuration. The application note provides a comprehensive approach to compensating the power output stage and managing large capacitive loads in ATE applications. By implementing the DFC technique, the design makes sure loop stability for composite amplifiers, improves system bandwidth, and optimizes performance - critical factors for supporting high-current ATE systems.

• Texas Instruments, OPA593 85-V, 250-mA Output Current, Precision, Power Op Amp, data sheet.
• Texas Instruments, Determine Optimal Isolation Resistance for Driving Capacitive Load, application note.
• Texas Instruments, Closed-Loop Analysis of Load-Induced Amplifier Stability Issues Using ZOUT, application note.
• Texas Instruments, Stability Analysis of Voltage-Feedback Op Amps, application note.
• Texas Instruments, OPA593 Evaluation Module.
• Texas Instruments, Precision Lab Series: Op Amps. training video.
• Texas Instruments, TINA-TI.