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LM15851 Ultra-Wideband RF Sampling Subsystem
SLAS990E
January 2014 – October 2017
LM15851
PRODUCTION DATA.
CONTENTS
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LM15851 Ultra-Wideband RF Sampling Subsystem
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Internal Characteristics
6.8
Switching Characteristics
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Signal Acquisition
7.3.2
The Analog Inputs
7.3.2.1
Input Clamp
7.3.2.2
AC Coupled Input Usage
7.3.2.3
DC Coupled Input Usage
7.3.2.4
Handling Single-Ended Input Signals
7.3.3
Clocking
7.3.4
Over-Range Function
7.3.5
ADC Core Features
7.3.5.1
The Reference Voltage
7.3.5.2
Common-Mode Voltage Generation
7.3.5.3
Bias Current Generation
7.3.5.4
Full Scale Range Adjust
7.3.5.5
Offset Adjust
7.3.5.6
Power-Down
7.3.5.7
Built-In Temperature Monitor Diode
7.3.6
Digital Down Converter (DDC)
7.3.6.1
NCO/Mixer
7.3.6.2
NCO Settings
7.3.6.2.1
NCO Frequency Phase Selection
7.3.6.2.2
NCO_0, NCO_1, and NCO_2 (NCO_x)
7.3.6.2.3
NCO_SEL Bits (2:0)
7.3.6.2.4
NCO Frequency Setting (Eight Total)
7.3.6.2.4.1
Basic NCO Frequency-Setting Mode
7.3.6.2.4.2
Rational NCO Frequency Setting Mode
7.3.6.2.5
NCO Phase-Offset Setting (Eight Total)
7.3.6.2.6
Programmable DDC Delay
7.3.6.3
Decimation Filters
7.3.6.4
DDC Output Data
7.3.6.5
Decimation Settings
7.3.6.5.1
Decimation Factor
7.3.6.5.2
DDC Gain Boost
7.3.7
Data Outputs
7.3.7.1
The Digital Outputs
7.3.7.2
JESD204B Interface Features and Settings
7.3.7.2.1
Scrambler Enable
7.3.7.2.2
Frames Per Multi-Frame (K-1)
7.3.7.2.3
DDR
7.3.7.2.4
JESD Enable
7.3.7.2.5
JESD Test Modes
7.3.7.2.6
Configurable Pre-Emphasis
7.3.7.2.7
Serial Output-Data Formatting
7.3.7.2.8
JESD204B Synchronization Features
7.3.7.2.9
SYSREF
7.3.7.2.10
SYNC~
7.3.7.2.11
Code-Group Synchronization
7.3.7.2.12
Multiple ADC Synchronization
7.4
Device Functional Modes
7.4.1
DDC Modes
7.4.2
Calibration
7.4.2.1
Foreground Calibration Mode
7.4.2.2
Background Calibration Mode
7.4.3
Timing Calibration Mode
7.4.4
Test-Pattern Modes
7.4.4.1
Serializer Test-Mode Details
7.4.4.2
PRBS Test Modes
7.4.4.3
Ramp Test Mode
7.4.4.4
Short and Long-Transport Test Mode
7.4.4.5
D21.5 Test Mode
7.4.4.6
K28.5 Test Mode
7.4.4.7
Repeated ILA Test Mode
7.4.4.8
Modified RPAT Test Mode
7.5
Programming
7.5.1
Using the Serial Interface
7.5.1.1
Streaming Mode
7.6
Register Map
7.6.1
Memory Map
7.6.2
Register Descriptions
7.6.2.1
Standard SPI-3.0 (0x000 to 0x00F)
7.6.2.1.1
Configuration A Register (address = 0x000) [reset = 0x3C]
7.6.2.1.2
Configuration B Register (address = 0x001) [reset = 0x00]
7.6.2.1.3
Device Configuration Register (address = 0x002) [reset = 0x00]
7.6.2.1.4
Chip Type Register (address = 0x003) [reset = 0x03]
7.6.2.1.5
Chip Version Register (address = 0x006) [reset = 0x13]
7.6.2.1.6
Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
7.6.2.2
User SPI Configuration (0x010 to 0x01F)
7.6.2.2.1
User SPI Configuration Register (address = 0x010) [reset = 0x00]
7.6.2.3
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
7.6.2.3.1
Power-On Reset Register (address = 0x021) [reset = 0x00]
7.6.2.3.2
I/O Gain 0 Register (address = 0x022) [reset = 0x40]
7.6.2.3.3
IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
7.6.2.3.4
I/O Offset 0 Register (address = 0x025) [reset = 0x40]
7.6.2.3.5
I/O Offset 1 Register (address = 0x026) [reset = 0x00]
7.6.2.4
Clock (0x030 to 0x03F)
7.6.2.4.1
Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
7.6.2.4.2
Clock Generator Status Register (address = 0x031) [reset = 0x07]
7.6.2.4.3
Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
7.6.2.4.4
Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
7.6.2.4.5
Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
7.6.2.5
Serializer (0x040 to 0x04F)
7.6.2.5.1
Serializer Configuration Register (address = 0x040) [reset = 0x04]
7.6.2.6
ADC Calibration (0x050 to 0x1FF)
7.6.2.6.1
Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
7.6.2.6.2
Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
7.6.2.6.3
Calibration Background Control Register (address = 0x057) [reset = 0x10]
7.6.2.6.4
ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
7.6.2.6.5
Calibration Vectors Register (address = 0x05A) [reset = 0x00]
7.6.2.6.6
Calibration Status Register (address = 0x05B) [reset = undefined]
7.6.2.6.7
Timing Calibration Register (address = 0x066) [reset = 0x02]
7.6.2.7
Digital Down Converter and JESD204B (0x200-0x27F)
7.6.2.7.1
Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
7.6.2.7.2
JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
7.6.2.7.3
JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
7.6.2.7.4
JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
7.6.2.7.5
JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
7.6.2.7.6
JESD204B and System Status Register (address = 0x205) [reset = Undefined]
7.6.2.7.7
Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
7.6.2.7.8
Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
7.6.2.7.9
Overrange Period Register (address = 0x208) [reset = 0x00]
7.6.2.7.10
DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
7.6.2.7.11
DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
7.6.2.7.12
Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
7.6.2.7.13
NCO Frequency (Preset x) Register (address = see ) [reset = see ]
7.6.2.7.14
NCO Phase (Preset x) Register (address = see ) [reset = see ]
7.6.2.7.15
DDC Delay (Preset x) Register (address = see ) [reset = see ]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
RF Sampling Receiver
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.3
Initialization Set-Up
8.3.1
JESD204B Startup Sequence
8.4
Dos and Don'ts
8.4.1
Common Application Pitfalls
9
Power Supply Recommendations
9.1
Supply Voltage
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Thermal Management
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.1.3
Device Nomenclature
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Community Resource
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
NKE|68
MPQS033A
サーマルパッド・メカニカル・データ
発注情報
slas990e_oa
slas990e_pm
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