SLLS804D March   2009  – August 2016 SN65HVDA540-5-Q1 , SN65HVDA540-Q1 , SN65HVDA541-5-Q1 , SN65HVDA541-Q1 , SN65HVDA542-5-Q1 , SN65HVDA542-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 TXD Dominant State Time Out
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Undervoltage Lockout and Unpowered Device
      5. 8.3.5 Floating Pins
      6. 8.3.6 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode (HVDA540)
      4. 8.4.4 Standby Mode With RXD Wake Up-Request (HVDA541)
        1. 8.4.4.1 RXD Wake Up Request Lock Out for Bus Stuck Dominant Fault (HVDA541)
      5. 8.4.5 Silent (Receive Only) Mode (HVDA542)
      6. 8.4.6 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level and Normal Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C
    • Device HBM ESD Classification Level 3A
    • Device CDM ESD Classification Level C6
    • Device MM ESD Classification Level M4
  • Meets or Exceeds the Requirements of ISO 11898-2 and ISO 11898-5
  • GIFT/ICT Compliant
  • ESD Protection up to ±12 kV (Human-Body Model) on Bus Pins
  • I/O Voltage Level Adapting
    • SN65HVDA54x: Adaptable I/O Voltage Range (VIO) From 3 V to 5.33 V
    • SN65HVDA54x-5: 5 V VCC Device Version
  • Operating Modes:
    • Normal Mode: All Devices
    • Low Power Standby Mode (VCC Not Required, Only VIO Supply Needed Saving System Power)
      • SN65HVDA540: No Wake Up
      • SN65HVDA541: RXD Wake Up Request
    • Silent (Receive Only) Mode: HVDA542
  • High Electromagnetic Compliance (EMC)
  • Protection
    • Undervoltage Protection on VIO and VCC
    • Bus-Fault Protection of –27 V to 40 V
    • TXD Dominant State Time Out
    • RXD Wake Up Request Lock Out on CAN Bus Stuck Dominant Fault (HVDA541)
    • Thermal Shutdown Protection
    • Power-Up/Down Glitch-Free Bus I/O
    • High Bus Input Impedance When Unpowered (No Bus Load)

2 Applications

  • SAE J2284 High-Speed CAN for Automotive Applications
  • SAE J1939 Standard Data Bus Interface
  • GMW3122 Dual-Wire CAN Physical Layer
  • ISO 11783 Standard Data Bus Interface
  • NMEA 2000 Standard Data Bus Interface

3 Description

The SN65HVDA54x-Q1 and SN65HVDA54x-5-Q1 devices, known as the HVDA54x and HVDA54x-5 respectively, are designed and qualified for use in automotive applications and meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network) Physical Layer standard (transceiver).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65HVDA54x-Q1, SN65HVDA54x-5-Q1 SOIC (8) 4.90 mm × 3.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

HVDA54x Functional Block Diagram

SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 fbd_lls804.gif
HVDA54x devices pin 5 is VIO. HVDA54x-5 devices pin 5 is NC and VIO is internally connected to VCC.

HVDA54x-5 Functional Block Diagram

SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 fbd_1_lls804.gif
HVDA54x-5 devices: VIO is internally connected to VCC