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  • SN74LVC16T245 16-bit Dual-Supply Bus Transceiver With Configurable Level-Shifting / Voltage Translation and Tri-State Outputs

    • SCES636B AUGUST   2005  – April 2015 SN74LVC16T245

      PRODUCTION DATA.  

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  • SN74LVC16T245 16-bit Dual-Supply Bus Transceiver With Configurable Level-Shifting / Voltage Translation and Tri-State Outputs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: VCCA = 1.8 V ±0.15 V
    7. 7.7  Switching Characteristics: VCCA = 2.5 V ±0.2 V
    8. 7.8  Switching Characteristics: VCCA = 3.3 V ±0.3 V
    9. 7.9  Switching Characteristics: VCCA = 5 V ±0.5 V
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
      2. 9.3.2 Support High-Speed Translation
      3. 9.3.3 Partial-Power-Down Mode Operation
      4. 9.3.4 VCC Isolation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Enable Times
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

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DATA SHEET

SN74LVC16T245 16-bit Dual-Supply Bus Transceiver With Configurable Level-Shifting / Voltage Translation and Tri-State Outputs

1 Features

  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22

2 Applications

  • Personal Electronics
  • Industrial
  • Enterprise
  • Telecom

3 Description

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC16T245 TSSOP (48) 12.50 mm × 6.10 mm
TVSOP (48) 9.70 mm × 4.40 mm
SSOP (48) 15.88 mm × 7.49 mm
BGA MICROSTAR JUNIOR (56) 7.00 mm × 4.50 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC16T245 ld_ces636.gif

4 Revision History

Changes from A Revision (October 2005) to B Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Description (continued)

The SN74LVC16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

6 Pin Configuration and Functions

DGG and DGV Packages
48-Pin TSSOP and TVSOP
(Top View)
SN74LVC16T245 po_ces636.gif
GQL and ZQL Packages
56-Pin BGA
(Top View)
SN74LVC16T245 gql_ces636.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DGG / DGV GQL / ZQL
1A1 47 B5 I/O Input/Output. Referenced to VCCA
1A2 46 B6 I/O Input/Output. Referenced to VCCA
1A3 44 C5 I/O Input/Output. Referenced to VCCA
1A4 43 C6 I/O Input/Output. Referenced to VCCA
1A5 41 D5 I/O Input/Output. Referenced to VCCA
1A6 40 D6 I/O Input/Output. Referenced to VCCA
1A7 38 E5 I/O Input/Output. Referenced to VCCA
1A8 37 E6 I/O Input/Output. Referenced to VCCA
1B1 2 B2 I/O Input/Output. Referenced to VCCB
1B2 3 B1 I/O Input/Output. Referenced to VCCB
1B3 5 C2 I/O Input/Output. Referenced to VCCB
1B4 6 C1 I/O Input/Output. Referenced to VCCB
1B5 8 D2 I/O Input/Output. Referenced to VCCB
1B6 9 D1 I/O Input/Output. Referenced to VCCB
1B7 11 E2 I/O Input/Output. Referenced to VCCB
1B8 12 E1 I/O Input/Output. Referenced to VCCB
1DIR 1 A1 I Direction-control signal
1OE 48 A6 I Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State mode. Referenced to VCCA
2A1 36 F6 I/O Input/Output. Referenced to VCCA
2A2 35 F5 I/O Input/Output. Referenced to VCCA
2A3 33 G6 I/O Input/Output. Referenced to VCCA
2A4 32 G5 I/O Input/Output. Referenced to VCCA
2A5 30 H6 I/O Input/Output. Referenced to VCCA
2A6 29 H5 I/O Input/Output. Referenced to VCCA
2A7 27 J6 I/O Input/Output. Referenced to VCCA
2A8 26 J5 I/O Input/Output. Referenced to VCCA
2B1 13 F1 I/O Input/Output. Referenced to VCCB
2B2 14 F2 I/O Input/Output. Referenced to VCCB
2B3 16 G1 I/O Input/Output. Referenced to VCCB
2B4 17 G2 I/O Input/Output. Referenced to VCCB
2B5 19 H1 I/O Input/Output. Referenced to VCCB
2B6 20 H2 I/O Input/Output. Referenced to VCCB
2B7 22 J1 I/O Input/Output. Referenced to VCCB
2B8 23 J2 I/O Input/Output. Referenced to VCCB
2DIR 24 K1 I Direction-control signal
2OE 25 K6 I Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State mode. Referenced to VCCA
GND 4 B3 — Ground
B4
10 D3
15 D4
21 G3
28 G4
34 J3
45 J4
NC(1) — A2 —
A3
A4
A5
K2
K3
K4
K5
VCCA 31 C4 — A-port supply. 1.65 V ≤ VCCA≤ 5.5 V
42 H4
VCCB 7 C3 — B-port supply. 1.65 V ≤ VCCB≤ 5.5 V
18 H3
(1) NC – No internal connection

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCA
VCCB		 Supply voltage –0.5 6.5 V
VI Input voltage(2) I/O ports (A port) –0.5 6.5 V
I/O ports (B port) –0.5 6.5
Control inputs –0.5 6.5
VO Voltage applied to any output
in the high-impedance or power-off state(2)		 A port –0.5 6.5 V
B port –0.5 6.5
VO Voltage applied to any output in the high or low state(2)(3) A port –0.5 VCCA + 0.5 V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through each VCCA, VCCB, and GND ±100 mA
TJ Junction temperature -40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input (VI ) and output (VO) negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (A115-A) ±200
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

See (1)(2)(3)(4)
VCCI VCCO MIN MAX UNIT
VCCA Supply voltage 1.65 5.5 V
VCCB 1.65 5.5
VIH High-level
input voltage		 Data inputs(5) 1.65 V to 1.95 V VCCI  × 0.65 V
2.3 V to 2.7 V 1.7
3 V to 3.6 V 2
4.5 V to 5.5 V VCCI  × 0.7
VIL Low-level
input voltage		 Data inputs(5) 1.65 V to 1.95 V VCCI  × 0.35 V
2.3 V to 2.7 V 0.7
3 V to 3.6 V 0.8
4.5 V to 5.5 V VCCI  × 0.3
VIH High-level
input voltage		 Control inputs
(referenced to VCCA)(6)		 1.65 V to 1.95 V VCCA  × 0.65 V
2.3 V to 2.7 V 1.7
3 V to 3.6 V 2
4.5 V to 5.5 V VCCA  × 0.7
VIL Low-level
input voltage		 Control inputs
(referenced to VCCA)(6)		 1.65 V to 1.95 V VCCA  × 0.35 V
2.3 V to 2.7 V 0.7
3 V to 3.6 V 0.8
4.5 V to 5.5 V VCCA  × 0.3
VI Input voltage Control inputs 0 5.5 V
VI/O Input/output voltage Active state 0 VCCO V
Tri-State 0 5.5
IOH High-level output current 1.65 V to 1.95 V –4 mA
2.3 V to 2.7 V –8
3 V to 3.6 V –24
4.5 V to 5.5 V –32
IOL Low-level output current 1.65 V to 1.95 V 4 mA
2.3 V to 2.7 V 8
3 V to 3.6 V 24
4.5 V to 5.5 V 32
Δt/Δv Input transition
rise or fall rate		 Data inputs 1.65 V to 1.95 V 20 ns/V
2.3 V to 2.7 V 20
3 V to 3.6 V 10
4.5 V to 5.5 V 5
TA Operating free-air temperature –40 85 °C
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(4) All unused data inputs of the device must be held at VCCA or GND to ensure proper device operation.
(5) For VCCI values not specified in the data sheet, VIH min = VCCI  × 0.7 V, VIL max = VCCI  × 0.3 V.
(6) For VCCA values not specified in the data sheet, VIH min = VCCA  × 0.7 V, VIL max = VCCA  × 0.3 V.

7.4 Thermal Information

THERMAL METRIC(1) SN74LVC16T245 UNIT
DL (SSOP) DGG (TSSOP) DGV (TVSOP) GQL / ZQL (BGA)
48 PINS 48 PINS 48 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance 92.9 60 82.5 64.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.5 13.9 34.2 16.6 °C/W
RθJB Junction-to-board thermal resistance 35.5 27.1 45.1 30.8 °C/W
ψJT Junction-to-top characterization parameter 8.1 0.5 2.7 0.9 °C/W
ψJB Junction-to-board characterization parameter 34.9 26.8 44.6 64.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS VCCA VCCB TA = 25°C TA = –40°C to 85°C UNIT
MIN TYP MAX MIN MAX
VOH IOH = –100 μA, VI = VIH 1.65 V to 4.5 V 1.65 V to 4.5 V VCCO  – 0.1 V
IOH = –4 mA, VI = VIH 1.65 V 1.65 V 1.2
IOH = –8 mA, VI = VIH 2.3 V 2.3 V 1.9
IOH = –24 mA, VI = VIH 3 V 3 V 2.4
IOH = –32 mA, VI = VIH 4.5 V 4.5 V 3.8
VOL IOL = 100 μA, VI = VIL 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 V
IOL = 4 mA, VI = VIL 1.65 V 1.65 V 0.45
IOL = 8 mA, VI = VIL 2.3 V 2.3 V 0.3
IOL = 24 mA, VI = VIL 3 V 3 V 0.55
IOL = 32 mA, VI = VIL 4.5 V 4.5 V 0.55
II Control inputs VI = VCCA or GND 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 μA
Ioff A or B
port		 VI or VO = 0 to 5.5 V 0 V 0 to 5.5 V ±1 ±2 μA
0 to 5.5 V 0 V ±1 ±2
IOZ A or B
port		 VO = VCCO or GND,
OE = VIH		 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 μA
ICCA VI = VCCI or GND,
IO = 0		 1.65 V to 5.5 V 1.65 V to 5.5 V 20 μA
5 V 0 V 20
0 V 5 V –2
ICCB VI = VCCI or GND,
IO = 0		 1.65 V to 5.5 V 1.65 V to 5.5 V 20 μA
5 V 0 V –2
0 V 5 V 20
ICCA + ICCB VI = VCCI or GND,
IO = 0		 1.65 V to 5.5 V 1.65 V to 5.5 V 30 μA
ΔICCA A port One A port at VCCA  – 0.6 V,
DIR at VCCA, B port = open		 3 V to 5.5 V 3 V to 5.5 V 50 μA
DIR DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND		 50
ΔICCB B port One B port at VCCB  – 0.6 V,
DIR at GND, A port = open		 3 V to 5.5 V 3 V to 5.5 V 50 μA
Ci Control
inputs		 VI = VCCA or GND 3.3 V 3.3 V 4 5 pF
Cio A or B
port		 VO = VCCA/B or GND 3.3 V 3.3 V 8.5 10 pF
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.

7.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V

over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCCB = 1.8 V
±0.15 V		 VCCB = 2.5 V
±0.2 V		 VCCB = 3.3 V
±0.3 V		 VCCB = 5 V
±0.5 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tPLH A B 1.7 21.9 1.3 9.2 1 7.4 0.8 7.1 ns
tPHL
tPLH B A 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns
tPHL
tPHZ OE A 1.6 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns
tPLZ
tPHZ OE B 2.4 32.2 1.9 13.1 1.7 12 1.3 10.3 ns
tPLZ
tPZH OE A 0.4 24 0.4 23.8 0.4 23.7 0.4 23.7 ns
tPZL
tPZH OE B 1.8 32 1.6 16 1.2 12.6 0.9 10.8 ns
tPZL

7.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V

over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCCB = 1.8 V
±0.15 V		 VCCB = 2.5 V
±0.2 V		 VCCB = 3.3 V
±0.3 V		 VCCB = 5 V
0.5 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tPLH A B 1.6 21.4 1.2 9 0.8 6.2 0.6 4.8 ns
tPHL
tPLH B A 1.2 9.3 1 9.1 1 8.9 0.9 8.8 ns
tPHL
tPHZ OE A 1.4 9 1.4 9 1.4 9 1.4 9 ns
tPLZ
tPHZ OE B 2.3 29.6 1.8 11 1.7 9.3 0.9 6.9 ns
tPLZ
tPZH OE A 1 10.9 1 10.9 1 10.9 1 10.9 ns
tPZL
tPZH OE B 1.7 28.2 1.6 12.9 1.2 9.4 1 6.9 ns
tPZL

7.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V

over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCCB = 1.8 V
±0.15 V		 VCCB = 2.5 V
±0.2 V		 VCCB = 3.3 V
±0.3 V		 VCCB = 5 V
±0.5 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tPLH A B 1.5 21.2 1.1 8.8 0.8 6.1 0.5 4.4 ns
tPHL
tPLH B A 0.9 7.2 0.8 6.2 0.7 6.1 0.6 6 ns
tPHL
tPHZ OE A 1.6 8.2 1.6 8.2 1.6 6.2 1.6 8.2 ns
tPLZ
tPHZ OE B 2.1 29 1.7 10.3 1.5 8.6 0.8 6.3 ns
tPLZ
tPZH OE A 0.8 7.8 0.8 7.8 0.8 7.8 0.8 7.8 ns
tPZL
tPZH OE B 1.6 27.7 1.4 12.4 1.1 8.5 0.9 8.4 ns
tPZL

7.9 Switching Characteristics: VCCA = 5 V ±0.5 V

over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC = 1.8 V
±0.15 V		 VCC = 2.5 V
±0.2 V		 VCC = 3.3 V
±0.3 V		 VCC = 5 V
±0.5 V		 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tPLH A B 1.6 21.4 1 8.8 0.7 6 0.4 4.2 ns
tPHL
tPLH B A 0.7 6.8 0.4 4.8 0.3 4.5 0.3 4.3 ns
tPHL
tPHZ OE A 0.3 5.4 0.3 5.4 0.3 5.4 0.3 6.4 ns
tPLZ
tPHZ OE B 2 28.7 1.6 9.7 1.4 8 0.7 5.7 ns
tPLZ
tPZH OE A 0.7 5.5 0.7 5.5 0.7 5.5 0.7 5.5 ns
tPZL
tPZH OE B 1.6 27.6 1.3 11.4 1 8.1 0.9 6 ns
tPZL

7.10 Operating Characteristics

TA = 25°C
PARAMETER TEST
CONDITIONS		 VCCA =
VCCB = 1.8 V		 VCCA =
VCCB = 2.5 V		 VCCA =
VCCB = 3.3 V		 VCCA =
VCCB = 5 V		 UNIT
TYP TYP TYP TYP
CpdA(1) A-port input, B-port output CL = 0,
f = 10 MHz,
tr = tf = 1 ns		 2 2 2 3 pF
B-port input, A-port output 18 19 19 22
CpdB(1) A-port input, B-port output 18 19 20 22
B-port input, A-port output 2 2 2 2
(1) Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation, SCAA035

7.11 Typical Characteristics

SN74LVC16T245 G001_sces584.gif
Figure 1. VOL Voltage vs IOL Current
SN74LVC16T245 G002_sces584.gif
Figure 2. VOH Voltage vs IOH Current

8 Parameter Measurement Information

SN74LVC16T245 pmi_ces636.gifFigure 3. Load Circuit and Voltage Waveforms

9 Detailed Description

9.1 Overview

The SN74LVC16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both A and B are in the high-impedance state.

This device is fully specified for partial-power-down applications using off output current (Ioff).

The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state.

9.2 Functional Block Diagram

SN74LVC16T245 ld2_ces635.gif

9.3 Feature Description

9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range

Both VCCA and VCCB can be supplied at any voltage from 1.65 V to 5.5 V making the device suitable for translating between any of the low voltage nodes (1.8-V, 2.5-V, and 3.3-V).

9.3.2 Support High-Speed Translation

SN74LVC16T245 can support high data rate application. Data rates can be calculated form the maximum propagation delay. This is also dependant on the output load. For example, for a 3.3-V to 5-V conversion, the maximum frequency is 200 MHz.

9.3.3 Partial-Power-Down Mode Operation

This device is fully specified for partial-power-down applications using off output current (Ioff). Ioff will prevent backflow current by disabling I/O output circuits when device is in partial power-down mode.

9.3.4 VCC Isolation

The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus.

9.4 Device Functional Modes

The functional modes for the SN74LVC16T245 device are shown in Table 1.

Table 1. Function Table(1)
(Each Transceiver)

CONTROL INPUTS OUTPUT CIRCUITS OPERATION
OE DIR A PORT B PORT
L L Enabled Hi-Z B data to A bus
L H Hi-Z Enabled A data to B bus
H X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os always are active.

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN74LVC16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74LVC16T245 device is ideal for data transmission where direction is different for each channel.

10.1.1 Enable Times

Calculate the enable times for the SN74LV16T245 using the following formulas:

Equation 1. tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
Equation 2. tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
Equation 3. tPZH (DIR to B) =tPLZ (DIR to A) + tPLH (A to B)
Equation 4. tPZL (DIR to B) = tPHZ(DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC16T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.

10.2 Typical Application

SN74LVC16T245 typapp_sces636.gifFigure 4. Typical Application Schematic

10.2.1 Design Requirements

This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. It is important that unused data inputs not be floating, as this can cause excessive internal leakage on the input CMOS structure. Make sure to tie any unused input and output ports directly to ground. For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Input voltage range 1.65 V to 5.5 V
Output voltage 1.65 V to 5.5 V

10.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
    • Use the supply voltage of the device that is driving the SN74LVC16T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
  • Output voltage range
    • Use the supply voltage of the device that the SN74LVC16T245 device is driving to determine the output voltage range.

10.2.3 Application Curve

SN74LVC16T245 G003_sces584.gifFigure 5. Translation Up (1.8 V to 5 V) at 2.5 MHz

11 Power Supply Recommendations

The SN74LVC16T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V and 3.3-V voltage nodes.

The output-enable OE input circuit is supplied by VCCA and when the OE input is high, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by the current-sinking capability of the driver.

12 Layout

12.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended.

  • Bypass capacitors should be used on power supplies.
  • Short trace lengths should be used to avoid excessive loading.
  • Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements.

12.2 Layout Example

SN74LVC16T245 layout-example-sces636.gifFigure 6. SN74LVC16T245 Layout Example

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

  • CMOS Power Consumption and Cpd Calculation, SCAA035
  • Implications of Slow or Floating CMOS Inputs, SCBA004

13.2 Trademarks

All other trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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