TMPx75-Q1 Automotive Grade Temperature Sensor With I2C and SMBus Interface in Industry-Standard LM75 Form Factor and Pinout

Table 1. Temperature Data Format

7.3.2.1 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted as a control signal.

When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high when SCL is high.

7.3.2.2 Serial Bus Address

To communicate with the TMP175-Q1 and TMP75-Q1, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation.

The TMP175-Q1 features three address pins to allow up to 27 devices to be addressed on a single bus interface. Table 2 describes the pin logic levels used to properly connect up to 27 devices. A 1 indicates that the pin is connected to the supply (VCC) and a 0 indicates that the pin is connected to GND; float indicates that the pin is left unconnected. The state of the A0, A1, and A2 pins is sampled on every bus communication and must be set prior to any activity on the interface.

The TMP75-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 3. The address pins of the TMP175-Q1 and TMP75-Q1 are read after reset, at start of communication, or in response to a two-wire address acquire request. After the state of the pins are read, the address is latched to minimize power dissipation associated with detection.

7.3.2.3 Writing and Reading to the TMP175-Q1 and TMP75-Q1

Accessing a particular register on the TMP175-Q1 and TMP75-Q1 devices is accomplished by writing the appropriate value to the Pointer register. The value for the Pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP175-Q1 and TMP75-Q1 requires a value for the Pointer register (see Figure 7).

When reading from the TMP175-Q1 and TMP75-Q1 devices, the last value stored in the Pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command; see Figure 9 for details of this sequence. If repeated reads from the same register are desired, the Pointer register bytes do not have to be continually sent because the TMP175-Q1 and TMP75-Q1 remember the Pointer register value until it is changed by the next write operation.

Register bytes are sent MSB first, followed by the LSB.

7.3.2.4 Slave Mode Operations

The TMP175-Q1 and TMP75-Q1 can operate as a slave receiver or slave transmitter.

7.3.2.5 SMBus Alert Function

The TMP175-Q1 and TMP75-Q1 support the SMBus alert function. When the TMP75-Q1 and TMP175-Q1 are operating in interrupt mode (TM = 1), the ALERT pin of the TMP75-Q1 or TMP175-Q1 can be connected as an SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP75-Q1 or TMP175-Q1 is active, the devices acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding T_HIGH or falling below T_LOW caused the ALERT condition. This bit is high if the temperature is greater than or equal to T_HIGH. This bit is low if the temperature is less than T_LOW; see Figure 10 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device clears its ALERT status. If the TMP75-Q1 or TMP175-Q1 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP75-Q1 or TMP175-Q1 loses the arbitration, its ALERT pin remains active.

7.3.2.6 General Call

The TMP175-Q1 and TMP75-Q1 respond to a two-wire, general-call address (0000000) if the eighth bit is 0. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins, but do not reset. If the second byte is 00000110, the TMP175-Q1 and TMP75-Q1 latches the status of their address pins and resets their internal registers to their power-up values.

7.3.2.7 High-Speed Mode

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP175-Q1 and TMP75-Q1 devices do not acknowledge this byte, but do switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP175-Q1 and TMP75-Q1 switch the input and output filter back to fast-mode operation.

7.3.2.8 Time-out Function

The TMP175-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START and STOP condition. The TMP175-Q1 releases the bus if it is pulled low and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL operating frequency.

7.3.3.1 Two-Wire Timing Diagrams

Figure 6. Two-Wire Timing Diagram

Figure 7. Two-Wire Timing Diagram for the TMP75-Q1 Write Word Format

Figure 8. Two-Wire Timing Diagram for the TMP175-Q1 Write Word Format

NOTE: Address pins A0, A1, and A2 = 0.

Figure 9. Two-Wire Timing Diagram for Read Word Format

NOTE: Address pins A0, A1, and A2 = 0.

Figure 10. Timing Diagram for SMBus ALERT

7.4.3.1 Comparator Mode (TM = 0)

In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the T_(HIGH) register and remains active until the temperature falls below the value in the T_(LOW) register. For more information on the comparator mode, see the High- and Low-Limit Registers section.

7.4.3.2 Interrupt Mode (TM = 1)

In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T_(HIGH) or goes below the T_(LOW) registers. The ALERT pin is cleared when the host controller reads the Temperature register. For more information on the interrupt mode, see the High- and Low-Limit Registers section.

Table 4. Pointer Register Byte (pointer = N/A) [reset = 00h]

Table 5. Pointer Addresses of the TMP175-Q1 and TMP75-Q1

Table 6. Byte 1 of the Temperature Register

Table 7. Byte 2 of the Temperature Register

Table 8. Configuration Register Format

7.5.3.1 Polarity (POL)

The Polarity bit of the TMP175-Q1 lets the user adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default), the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes active high and the state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is shown in Figure 12.

Figure 12. Output Transfer Function Diagrams

7.5.3.2 Fault Queue (F1/F0)

A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the T_HIGH and T_LOW registers. Additionally, the number of fault conditions required to generate an alert can be programmed using the fault queue. The fault queue is provided to prevent a false alert resulting from environmental noise. The fault queue requires consecutive fault measurements in order to trigger the Alert function. Table 9 defines the number of measured faults that can be programmed to trigger an Alert condition in the device. For the T_HIGH and T_LOW register format and byte order, see the High- and Low-Limit Registers section.

7.5.3.3 Converter Resolution (R1/R0)

The Converter Resolution bits control the resolution of the internal analog-to-digital (ADC) converter. This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 10 identifies the resolution bits and the relationship between resolution and conversion time.

Table 11. Byte 1 of the T_HIGH Register

Table 12. Byte 2 of the T_HIGH Register

Table 13. Byte 1 of the T_LOW Register

Table 14. Byte 2 of the T_LOW Register