TPS53647 4-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load
- SLUSC39B June 2015 – February 2017 TPS53647
  
  PRODUCTION DATA.

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DATA SHEET

TPS53647 4-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load

1 Features

8-bit Selectable BOOT Voltage via Pinstrap or NVM: 0.5 V to 2.5 V (down to 5-mV Step)
1-, 2-, 3-, or 4- Phase Operation
PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
1.8-V and 3.3-V PMBus Bias Compatible
Fault Reporting: Output Voltage, Output Current, and Temperature
Configurable with Non-Volatile Memory (NVM) or Resistor Pinstrap
16 Levels of Programmable OCP with Pinstrap or NVM
Fast Transient with DCAP+™Control
Optimized Efficiency at Light and Heavy Loads
Support Pre-Bias Startup
Phase Current Imbalance Detection and Reporting
8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
Driverless Configuration for Efficient High-Frequency Switching
Fully Compatible with CSD95372BQ5MC NexFET™ Power Stage
Accurate, Adjustable Voltage Positioning
300-kHz to 1-MHz Frequency Selections with Closed-loop Frequency Control
Patented AutoBalance™ Phase Balancing
Uses TI’s Fusion Digital Power Designer GUI
Dynamic Phase Shedding with Programmable Current Threshold
Conversion Voltage Range: 4.5 V to 17 V
Small, 6 mm × 6 mm, 40-Pin, QFN, PowerPAD™ Package

2 Applications

Application-Specific Integrated Circuit (ASIC) Power in Communications Equipment
High Density Power Solutions
Server Power
Smart Power Systems

3 Description

The TPS53647 is a high-current, multi-phase, step-down controller. The device offers built-in non volatile memory (NVM) and PMBus interface. It is compatible with the NexFET power stages (CSD95372BQ5MC). The TPS53647 provides 8-bit BOOT voltage selection covering output voltage from 0.5 V to 2.5 V, with steps as small as 5 mV, which is ideal for high current application with accurate output voltage setting. Advanced control features such as D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance, and high efficiency. The TPS53647 also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at light loads. In addition, the TPS53647 supports the PMBus communication interface with systems for telemetry of voltage, current, power, temperature, and fault conditions. Some of the configurations can be programmed by pinstrap or PMBus and stored in non-volatile memory to minimize the external component count.

The TPS53647 is offered in a space saving, thermally enhanced 40-pin QFN package and is rated to operate from –40°C to 125°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS53647	QFN (40)	6.00 mm × 6.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

TPS53647 fp_simp_app_tps53647_slusc39.gif

4 Revision History

Changes from A Revision (September 2016) to B Revision

Updated V3R3 LDO sectionGo
Added temperature default value VR_HOT and VR_FAULT Indication sectionGo
Corrected factory default value of VOUT_OV_FAULT_RESPONSE command in Table 7Go
Corrected factory default value of VIN_OV_FAULT_LIMIT command in Table 7Go
Corrected factory default value of MFR_ID command in Table 7Go
Corrected factory default value of MFR_SPECIFIC_44 command in Table 7Go

Changes from * Revision (June 2015) to A Revision

Updated the V_ADDR-TRISE condition of the PADDR specification in the Electrical Characteristics table from "1.647 V" to "1.615 V" Go
Updated the V_OCL-R condition of the I_OCLx specification in the Electrical Characteristics table from "0.8 V" to "0.85 V" Go
Updated the V_OCL-R condition of the I_OCLx specification in the Electrical Characteristics table from "1.0 V" to "0.95 V" Go
Updated the V_OCL-R condition of the V_RAMP specification in the Electrical Characteristics table to "±50 mV" Go
Updated the V_SLEW-MODE condition of the V_MODE specification in the Electrical Characteristics table from " 1.647 V with ±20 mV tolerance" to "1.615 V with ±10 mV tolerance" Go
Updated the V_O-USR condition of the V_USR specification in the Electrical Characteristics table from " V_O-USR ≥ 1.55 V (USR OFF)" to "1.55 V ≤ V_O-USR ≤ 1.6 V " Go
Updated the V_VBOOT (B₇B₆B₅B₄) condition of the V_BOOT specification in the Electrical Characteristics table from " 1.647 V with ±20 mV tolerance" to "1.615 V with ±10 mV tolerance" Go
Clarified the READ_VIN (88h) sectionGo
Corrected typographical error in READ_VOUT (8Bh) sectionGo
Clarified the READ_IOUT (8Ch) sectionGo
Clarified the READ_TEMPERATURE_1 (8Dh) sectionGo
Clarified the READ_POUT (96h) sectionGo
Clarified the READ_POUT (96h) sectionGo
Clarified the MFR_SPECIFIC_04 (Read VOUT) (D4h) sectionGo
Updated the MFR_SPECIFIC_14 (Ramp Height) (DEh) sectionGo
Clarified the Set the Load-Line sectionGo
Updated Table 79Go
Updated Table 82 Go
Added Receiving Notification of Documentation Updates sectionGo
Added Community Resources sectionGo

5 Pin Configuration and Functions

RTA Package

40-Pin QFN

Top View

NC = No internal connection

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
ADDR-TRISE	28	I	Voltage divider to VREF pin. A resistor (R_ADDR-TRISE) connected between this pin and GND sets the 3-bits. Bit 2 and bit 1 set the rise slew rate. Bit 0 Selects the LSB of BOOT voltage. The voltage (V_ADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up.
COMP	11	O	Output of the g_M error amplifier. Resistors and capacitors connected between this pin and the VREF pin set the compensation.
CSP1	3	I	Positive current sense inputs. Connect to the IOUT pin of TI smart power stages (ex: CSD95372BQ5MC). Tie CSP4, CSP3, or CSP2 to the V3R3 pin according to Table 3 to disable the corresponding phase.
CSP2	4
CSP3	5
CSP4	6
ENABLE	23	I	VR enable. 1-V I/O level; 100-ns debounce.
F-IMAX	32	I	Voltage divider to VREF pin. A resistor (R_F-IMAX) connected between this pin and GND sets the operating frequency of the controller. The voltage level (V_F-IMAX) sets the maximum operating current of the converter. The IMAX value is an 8-bit A/D where V_F-IMAX = V_VREF × I_MAX / 255. Both are latched at V3R3 power-up.
GND	17	G	Ground pin.
GND	20	G	Connect these pins to GND. Note this is not IC ground pin.
GND	22	G	Connect these pins to GND. Note this is not IC ground pin.
IMON	2	O	Analog current monitor output.
ISUM	12	O	A resistor (R_ISUM) connected between this pin and VREF pin determines the droop. (where n is the number of phases)
NC	7	—	No connection. Leave the pin open or pull up to V3R3 pin.
	8	—	No connection. Leave the pin open or pull up to V3R3 pin.
	33	—	No connection.
	34	—	No connection.
OCL-R	1	I	A resistor (R_OCL-R) connected between this pin and GND and the voltage level (V_OCL-R) select 1 of 16 OCL levels (per phase current-limit). V_OCL-R also sets one of four RAMP levels. The device latches these settings when V3R3 powers up.
O-USR	30	I	Voltage divider to VREF pin. A resistor (R_O-USR) connected between this pin and GND selects one of seven OSR thresholds or OFF. The voltage level (V_O-USR) sets one of seven USR levels or OFF. The device latches these settings when V3R3 powers up.
PMB_ALERT	25	O	I²C PMBus interrupt line. Open drain. 3.3-V and 1.8-V logic level.
PMB_CLK	24	I	I²C PMBus clock. 3.3-V and 1.8-V logic level.
PMB_DIO	26	I/O	I²C PMBus digital I/O line. 3.3-V and 1.8-V logic level.
PWM1	38	O	PWM signals for each phase
PWM2	37
PWM3	36
PWM4	35
RESET	21	I	Reset pin. If this pin is low for more than 1000 ns, the controller pulls the output voltage to the V_BOOT level.
SKIP-NVM	39	O	A resistor (R_SKIP-NVM) connected between this pin and GND sets either pinstrap or NVM configuration mode. This pin can also connect to the FCCM pin of TI smart power stages (ex: CSD95372BQ5MC) for SKIP or FCCM operation.
SLEW-MODE	29	I	Voltage divider to VREF pin. A resistor (R_SLEW-MODE) connected between this pin and GND sets 8 slew rates. The voltage level (V_SLEW-MODE) sets 4-bit operation modes. Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5). Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase interleaving; 0 for 4 phase interleaving individually). Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable). Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The device latches these settings when V3R3 powers up.
TSEN	40	I	Connect to the TAO/FAULT pin of TI smart power stages (ex: CSD95372BQ5MC) to sense the highest temperature of the power stages and to sense the fault signal from the power stages.
V3R3	14	O	3.3-V LDO output. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger.
V5	15	P	5-V power input. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. This pin is used to power all internal analog circuits.
VBOOT	31	I	Voltage divider to VREF pin. A resistor (R_VBOOT) connected between this pin and GND sets 3 bits (B[3:1]). The voltage level (V_VBOOT) sets 4 bits (B[7:4]). The total 7 bits set 7 of 8 bits of VID of boot voltage (B[7:1]). The device latches these settings when V3R3 powers up.
VIN	16	P	Input voltage supply. This pin is also used for input voltage sensing for on-time control and input undervoltage lockout (UVLO).
VR_RDY	18	O	Power good open-drain output for the controller. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger.
VR_FAULT	27	O	VR fault indicator (open-drain). The failures include shorts of the high-side FETs, over temperature, output overvoltage, and overcurrent conditions of the input. The fault signal should be used on the platform to remove the power source either by firing a shunting SCR to blow a fuse or by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is LOW. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VR_HOT	19	O	Thermal flag open drain output. Active low. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VREF	13	O	1.7-V, 500-µA, LDO reference voltage. Bypass this pin to GND with a ceramic capacitor with a value of 0.33 µF. Connect the VREF pin to the REFIN pin of TI smart power stages (ex: CSD95372BQ5MC) as the current-sense reference voltage.
VSN	10	I	Negative input of the remote voltage sense amplifier. Connect this pin directly to the GND of the load.
VSP	9	I	Positive input of the remote voltage sense amplifier. Connect this pin directly to the load.
Thermal Pad		GND	Thermal pad. Connect the thermal pad to the ground plane with multiple vias.

(1) I = Input, O = Output, P = Power, I/O = Bi-directional, GND = ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾ ⁽²⁾

		MIN	MAX	UNIT
Input Voltage	VIN	–0.3	19	V
	V5	–0.3	6
	ADDR-TRISE, CSP1, CSP2, CSP3, CSP4, ENABLE, F-IMAX, OCL-R, O-USR, PMB_CLK, PMB_DIO, RESET, SLEW-MODE, VBOOT, VSP	–0.3	3.6
	TSEN	–0.3	6
	GND, VSN	–0.3	0.3
Output Voltage	VREF	–0.3	1.8	V
	IMON, ISUM,PMB_ALERT, PWM1, PWM2, PWM3, PWM4, SKIP-NVM, V3R3, VR_RDY, VR_FAULT, VR_HOT	–0.3	3.6
	COMP	–0.3	6
Operating Junction Temperature, T_J		–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	-2.5	2.5	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	-1.5	1.5	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_I	Input voltage	VIN	4.5	12	17	V
		TSEN	-0.1		5.5
		V5	4.5	5	5.5
		ADDR-TRISE, F-IMAX, OCL-R, O-USR, SLEW-MODE, VBOOT	0.1		V_VREF
		CSP1, CSP2, CSP3, CSP4, VSP	–0.1		2.5
		ENABLE, PMB_CLK, PMB_DIO	–0.1		3.5
		GND, VSN	–0.1		0.1
V_O	Output voltage	VREF	–0.1		1.72	V
		V3R3	-0.1	3.3	3.5
		IMON, ISUM, PMB_ALERT, PWM1, PWM2, PWM3, PWM4, SKIP-NVM, VR_RDY, VR_FAULT, VR_HOT	–0.1		3.5
		COMP	–0.1		5.5
T_A	Operating free air temperature		–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS53647	UNIT
		RTA (QFN)
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	30.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.2
R_θJB	Junction-to-board thermal resistance	6.9
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	6.8
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, V_VIN = 12 V, V_V5 = 5 V, V_VSN = GND, V_VSP = V_OUT (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY: CURRENTS, UVLO, AND POWER-ON RESET
I_VIN	VIN supply current, 4-phase active	V_VDAC < V_VSP < V_VDAC + 100 mV, ENABLE = HI			115	µA
I_V5	V5 supply current	PMBus Idle, ENABLE = HI		6.1	7	mA
I_V5SBY	V5 standby current	ENABLE = LO		2	2.6	mA
V_V3R3	V3R3 output voltage	I_V3R3 = 0 A	3.2	3.3	3.4	V
V_{V3R3(dropout)}	V3R3 load regulation	I_V3R3 = 5 mA			100	mV
V_V5UVLOH	V5 UVLO OK threshold	Ramp up	4.1	4.25	4.5	V
V_V5UVLOL	V5 UVLO fault threshold	Ramp down	3.95	4.05	4.25	V
V_HYS(V5)	V5 UVLO hysteresis	Hysteresis	0.15	0.23	0.3	V
V_VINUVLO	VIN UVLO voltage	MFR_SPEC_16[1:0] = 00	4.2	4.5	4.7	V
		MFR_SPEC_16[1:0] = 01	6.9	7.25	7.45
		MFR_SPEC_16[1:0] = 10	8.6	9.0	9.25
		MFR_SPEC_16[1:0] = 11	9.8	10.3	10.7
V_HYS(VIN)	VIN UVLO hysteresis voltage	Hysteresis voltage		1		V
REFERENCES: DAC AND VREF
V_VIDSTP	VID Step size	VR12.5: Change VID0 HI to LO to HI		10		mV
V_VIDSTP	VID Step size	VR12.0: Change VID0 HI to LO to HI		5		mV
V_DAC1	Closed Loop VSP tolerance	VR12.0: 0.61 V ≤ V_VSP ≤ 0.995 V, I_OUT = 0 A , 0 °C ≤ T_A≤ 85 °C	–6		6.5	mV
V_DAC2	Closed Loop VSP tolerance	VR12.0: 1 V ≤ V_VSP ≤ 1.52 V, I_COUT = 0 A, 0 °C ≤ T_A≤ 85 °C	–0.6		0.6	%
V_DAC3	Closed Loop VSP tolerance	VR12.5: 1.50V ≤ V_VSP ≤ 2.50 V, I_OUT = 0 A, 0 °C ≤ T_A≤ 85 °C	–1		1	%
V_DAC4	Closed Loop VSP tolerance	VR12.0: 0.61 V ≤ V_VSP ≤ 0.995 V, I_OUT = 0 A, –40°C ≤ T_A≤ 125 °C	–8		8	mV
V_DAC5	Closed Loop VSP tolerance	VR12.0: 1.0 V ≤ V_VSP ≤ 1.52 V, I_OUT = 0 A, –40 °C ≤ T_A≤ 125 °C	-0.8		0.8	%
V_DAC6	Closed Loop VSP tolerance	VR12.5: 1.50 V ≤ V_VSP ≤ 2.50V, I_OUT = 0 A, –40°C ≤ T_A≤ 125 °C	-1.1		1.0	%
V_VREF	VREF output	4.5 ≤ V_V5 ≤ 5.5 V, I_VREF = 0 A	1.685	1.70	1.717	V
V_VREFSRC	VREF output source	I_VREF = 0 to 500 µA	–4	-1		mV
V_VREFSNK	VREF output sink	I_VREF = –500 to 0 µA		1	4	mV
CURRENT SENSE: AMPLIFIER AND PHASE BALANCING
G_CSINT	Internal current sense gain	Gain from (CSPx – VREF ) to PWM comparator		1.0		V/V
COMPENSATOR: VOLTAGE POSITIONING AND AMPLIFIER
g_M(isum)	ISUM amplifier transconductance	V_VSP = 1.7 V		500		µS
g_M(comp)	COMP amplifier transconductance	V_VSP = 1.7 V		1000		µS
V_CCLAMPN	COMP amplifier negative clamp voltage	(V_VREF– V_COMP)		V_RAMP+ 20		mV
V_CCLAMPP	COMP amplifier positive clamp voltage	(V_COMP– V_VREF)	2.1	2.2	2.3	V
VOLTAGE SENSE: VSP AND VSN
I_VSP	VSP input bias current	Not in fault, disable or UVLO, V_VSP = V_VDAC = 2.3 V, V_VSN = 0 V			300	µA
I_VSN	VSN input bias current	Not in fault, disable or UVLO, V_VSP = V_VDAC = 2.3 V, V_VSN = 0 V	-30	-23		µA
R_SFTSTP	Transistor resistance	Connect to VSP		10		kΩ
LOGIC ( RESET, VR_RDY, VR_FAULT, VR_HOT, AND ENABLE) INTERFACE PINS: I/O VOLTAGE AND CURRENT
R_RPGDL	Open drain pull-down resistance	VR_RDY, pulldown resistance at 0.31 V		36	50	Ω
I_VRTTLK	Open drain leakage current	VR_HOT, VR_RDY, hi-Z leakage, apply 3.3 V in off state	–2	0.2	2	µA
V_RSTL	RESET logic low	RESET Pin			0.8	V
V_RSTH	RESET logic high	RESET Pin	1.2			V
T_RSTTDLY	RESET Delay Time			1		µs
V_ENL	ENABLE logic low				0.3	V
V_ENH	ENABLE logic high		0.8			V
I_ENH	I/O 1.1- V leakage	Leakage current , V_ENABLE = 1.1 V			25	µA
PMBUS INTERFACE PINS: I/O VOLTAGE AND CURRENT
V_PMBL	PMBus pins logic low				0.8	V
V_PMBH	PMBus pins logic high		1.2			V
I_PMBL	Logic low input current	V_PMBus=0 V	-10		10	µA
I_PMBH	Logic high input current	V_PMBus=1.8 V	-10		10	µA
ADDR-TRISE PIN: PMBUS ADDRESS, SOFT START RISE TIME SETTING
SL_RISE	Soft start rise slew rate in terms of V_OUT slew rate	R_ADDR-TRISE ≤ 20 kΩ or R_ADDR-TRISE = 24 kΩ or MFR_SPEC_12<1:0> = 00b		1
		R_ADDR-TRISE = 30 kΩ or R_ADDR-TRISE = 39 kΩ or MFR_SPEC_12<1:0> = 01b		1/2
		R_ADDR-TRISE = 56 kΩ or R_ADDR-TRISE = 75 kΩ or MFR_SPEC_12<1:0> = 10b		1/4
		R_ADDR-TRISE = 100 kΩ or R_ADDR-TRISE = 150 kΩ or MFR_SPEC_12<1:0> = 11b		1/8
BOOT	BOOT voltage set (B0)	R_ADDR-TRISE ≤ 20 kΩ or R_ADDR-TRISE = 30 kΩ or R_ADDR-TRISE = 56 kΩ or R_ADDR-TRISE = 100 kΩ, or MFR_SPEC_11 [0] = 0b		0
BOOT	BOOT voltage set (B0)	R_ADDR-TRISE = 24 kΩ or R_ADDR-TRISE = 39 kΩ or R_ADDR-TRISE = 75 kΩ or R_ADDR-TRISE = 150 kΩ, or MFR_SPEC_11 [0] = 1b		1
PADDR	PMBus address bits set (11P₄0P₂P₁P₀)	V_ADDR-TRISE ≤ 0.053 V with ±20 mV tolerance		1100000
		V_ADDR-TRISE = 0.159 V with ±20 mV tolerance		1100001
		V_ADDR-TRISE = 0.266 V with ±20 mV tolerance		1100010
		V_ADDR-TRISE = 0.372 V with ±20 mV tolerance		1100011
		V_ADDR-TRISE = 0.478 V with ±20 mV tolerance		1100100
		V_ADDR-TRISE = 0.584 V with ±20 mV tolerance		1100101
		V_ADDR-TRISE = 0.691 V with ±20 mV tolerance		1100110
		V_ADDR-TRISE = 0.797 V with ±20 mV tolerance		1100111
		V_ADDR-TRISE = 0.903 V with ±20 mV tolerance		1110000
		V_ADDR-TRISE = 1.009 V with ±20 mV tolerance		1110001
		V_ADDR-TRISE = 1.116 V with ±20 mV tolerance		1110010
		V_ADDR-TRISE = 1.222 V with ±20 mV tolerance		1110011
		V_ADDR-TRISE = 1.328 V with ±20 mV tolerance		1110100
		V_ADDR-TRISE = 1.434 V with ±20 mV tolerance		1110101
		V_ADDR-TRISE = 1.541 V with ±20 mV tolerance		1110110
		V_ADDR-TRISE = 1.615 V with ±10 mV tolerance		1110111
OCL-R PIN: OVERCURRENT THRESHOLDS AND RAMP SETTINGS
I_OCLx	Phase OCL level (CSPx-VREF) (valley current-limit)	R_OCL-R = 20 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0000b	21	24	27	A
		R_OCL-R = 24 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0001b	25	27	30
		R_OCL-R = 30 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0010b	28	30	33
		R_OCL-R = 39 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0011b	31	33	36
		R_OCL-R = 56 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0100b	34	36	39
		R_OCL-R = 75 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0101b	37	39	42
		R_OCL-R = 100 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0110b	40	42	45
		R_OCL-R ≥ 150 kΩ and V_OCL-R ≤ 0.85 V or MFR_SPEC_00[3:0] = 0111b	43	45	48
		R_OCL-R = 20 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1000b	46	48	51
		R_OCL-R = 24 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1001b	49	51	54
		R_OCL-R = 30 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1010b	52	54	57
		R_OCL-R = 39 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1011b	55	57	60
		R_OCL-R = 56 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1100b	58	60	63
		R_OCL-R = 75 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1101b	61	63	66
		R_OCL-R = 100 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1110b	64	66	69
		R_OCL-R ≥ 150 kΩ and V_OCL-R ≥ 0.95 V or MFR_SPEC_00[3:0] = 1111b	67	69	72
V_RAMP	Ramp setting	V_OCL-R = 0.2 V ±50mV or V_OCL-R = 1.0 V ±50mV or MFR_SPEC_14[2:0] = 001b	30	40	50	mV_{P_P}
		V_OCL-R = 0.4 V ±50mV or V_OCL-R = 1.2 V ±50mV or MFR_SPEC_14[2:0] = 011b	70	80	90
		V_OCL-R = 0.6 V ±50mV or V_OCL-R = 1.4 V ±50mV or MFR_SPEC_14[2:0] = 110b	135	145	155
		V_OCL-R = 0.8 V ±50mV or V_OCL-R = 1.6 V ±50mV or MFR_SPEC_14[2:0] = 111b	180	190	205
F-IMAX PIN: FREQUENCY AND IMAX SETTINGS
f_SW	Switching frequency (See Switching Characteristics)
I_MAX	IMAX values	V_F-IMAX(min) = 0.136V I_MAX=(V_F-IMAX /V_VREF × 256)-0.5	18	20	22	A
		V_F-IMAX(min) = 0.403 V I_MAX=(V_F-IMAX /V_VREF × 256)-0.5	58	60	62
		V_F-IMAX(min) = 0.536 V I_MAX=(V_F-IMAX /V_VREF × 256)-0.5	78	80	82
		V_F-IMAX(min) = 0.803 V I_MAX=(V_F-IMAX /V_VREF × 256)-0.5	118	120	122
SLEW-MODE PIN: SLEW RATES and MODE SELECTIONS
SL_SET	Slew rate setting	R_SLEW-MODE ≤ 20 kΩ or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 0b	0.28	0.34		mV/µs
		R_SLEW-MODE = 24 kΩ or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 0b	0.60	0.68
		R_SLEW-MODE = 30 kΩ or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 0b	0.91	1.02
		R_SLEW-MODE = 39 kΩ or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 0b	1.22	1.36
		R_SLEW-MODE = 56 kΩ or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 0b	1.53	1.7
		R_SLEW-MODE = 75 kΩ or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 0b	1.85	2.04
		R_SLEW-MODE = 100 kΩ or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 0b	2.16	2.38
		R_SLEW-MODE≥ 150 kΩ or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 0b	2.48	2.74
		R_SLEW-MODE ≤ 20 kΩ or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 1b	1.53	1.7
		R_SLEW-MODE = 24 kΩ or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 1b	1.85	2.04
		R_SLEW-MODE = 30 kΩ or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 1b	2.16	2.38
		R_SLEW-MODE = 39 kΩ or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 1b	2.48	2.74
		R_SLEW-MODE = 56 kΩ or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 1b	2.79	3.08
		R_SLEW-MODE = 75 kΩ or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 1b	3.10	3.43
		R_SLEW-MODE = 100 kΩ or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 1b	3.41	3.76
		R_SLEW-MODE≥ 150 kΩ or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 1b	3.73	4.13
MODE	MODE bits set⁽¹⁾ (M₃M₂M₁M₀)	V_SLEW-MODE ≤ 0.053 V with ±20 mV tolerance, or MFR_SPEC_13[7:3] = 00x00		0000
		V_SLEW-MODE = 0.159 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 00x01b		0001
		V_SLEW-MODE = 0.266 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 00x10b		0010
		V_SLEW-MODE = 0.372V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 00x11b		0011
		V_SLEW-MODE = 0.478 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 01x00b		0100
		V_SLEW-MODE = 0.584V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 01x01b		0101
		V_SLEW-MODE = 0.691 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 01x10b		0110
		V_SLEW-MODE = 0.797 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 01x11b		0111
		V_SLEW-MODE = 0.903 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 10x00b		1000
		V_SLEW-MODE = 1.009 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 10x01b		1001
		V_SLEW-MODE = 1.116 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 10x10b		1010
		V_SLEW-MODE = 1.222 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 10x11b		1011
		V_SLEW-MODE = 1.328 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 11x00b		1100
		V_SLEW-MODE = 1.434 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 11x01b		1101
		V_SLEW-MODE = 1.541 V with ±20 mV tolerance, MFR_SPEC_13[7:3] = 11x10b		1110
		V_SLEW-MODE = 1.615 V with ±10 mV tolerance, MFR_SPEC_13[7:3] = 11x11b		1111
O-USR PIN: OVERSHOOT AND UNDERSHOOT REDUCTION THRESHOLD SETTING
V_OSR	OSR voltage setting	R_O-USR ≤ 20 kΩ or MFR_SPEC_09 [2:0] = 000b	20	30	40	mV
		R_O-USR = 24 kΩ or MFR_SPEC_09 [2:0] = 001b	30	40	50
		R_O-USR = 30 kΩ or MFR_SPEC_09 [2:0] = 010b	50	60	70
		R_O-USR = 39 kΩ or MFR_SPEC_09 [2:0] = 011b	70	80	90
		R_O-USR = 56 kΩ or MFR_SPEC_09 [2:0] = 100b	90	100	110
		R_O-USR = 75 kΩ or MFR_SPEC_09 [2:0] = 101b	110	120	130
		R_O-USR = 100 kΩ or MFR_SPEC_09 [2:0] = 110b	130	140	150
		R_O-USR ≥ 150 kΩ or MFR_SPEC_09 [2:0] = 111b		OFF
V_USR	USR voltage setting	V_O-USR = 0.2 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 000b	10	20	30	mV
		V_O-USR = 0.4 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 001b	20	30	40
		V_O-USR = 0.6 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 010b	50	60	70
		V_O-USR = 0.8 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 011b	70	80	90
		V_O-USR = 1.0 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 100b	90	100	110
		V_O-USR = 1.2 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 101b	110	120	130
		V_O-USR = 1.4 V with ±50 mV tolerance or MFR_SPEC_09 [6:4] = 110b	130	140	150
		1.55 V ≤ V_O-USR ≤ 1.6 V or MFR_SPEC_09 [6:4] = 111b		OFF
V_OSRHYS	OSR voltage hysteresis⁽¹⁾	All settings		10		mV
V_USRHYS	USR voltage hysteresis⁽¹⁾	All settings		10		mV
VBOOT PIN: BOOT VOLTAGE SETTING
V_BOOT ⁽¹⁾	BOOT voltage setting (B₃B₂B₁)	R_VBOOT ≤ 20 kΩ, or MFR_SPEC_11 [3:1] = 000b		000
		R_VBOOT = 24 kΩ, or MFR_SPEC_11 [3:1] = 001b		001
		R_VBOOT = 30 kΩ, or MFR_SPEC_11 [3:1] = 010b		010
		R_VBOOT = 39 kΩ, or MFR_SPEC_11 [3:1] = 011b		011
		R_VBOOT = 56 kΩ, or MFR_SPEC_11 [3:1] = 100b		100
		R_VBOOT = 75 kΩ, or MFR_SPEC_11 [3:1] = 101b		101
		R_VBOOT = 100 kΩ, or MFR_SPEC_11 [3:1] = 110b		110
		R_VBOOT ≥ 150 kΩ, or MFR_SPEC_11 [3:1] = 111b		111
	BOOT voltage setting (B₇B₆B₅B₄)	V_VBOOT ≤ 0.053 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0000b		0000
		V_VBOOT = 0.159 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0001b		0001
		V_VBOOT= 0.266 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0010b		0010
		V_VBOOT = 0.372 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0011b		0011
		V_VBOOT = 0.478 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0100b		0100
		V_VBOOT = 0.584 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0101b		0101
		V_VBOOT = 0.691 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0110b		0110
		V_VBOOT = 0.797 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0111b		0111
		V_VBOOT = 0.903 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1000b		1000
		V_VBOOT = 1.009 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1001b		1001
		V_VBOOT = 1.116 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1010b		1010
		V_VBOOT = 1.222 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1011b		1011
		V_VBOOT = 1.328 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1100b		1100
		V_VBOOT = 1.434 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1101b		1101
		V_VBOOT = 1.541 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1110b		1110
		V_VBOOT = 1.615 V with ±10 mV tolerance, or MFR_SPEC_11 [7:4] = 1111b		1111
PROTECTION: OVP, UVP, VR_RDY
V_OVPFP	Pre-bias OVP voltage threshold⁽¹⁾	ENABLE is low and V_VSP> V_OVPFP, PWM → LO		2.75		V
V_OVPF5	Fixed OVP voltage threshold (VR12.5)	ENABLE is high and (V_VSP–V_VSN) > V_OVPH5 for 1 μs, PWM → LO, V_OUT(max) ≤ 1.8 V		2.2		V
		1.8 V < V_OUT(max) ≤ 2.0 V		2.4
		2.0 V < V_OUT(max) ≤ 2.2 V		2.6
		V_OUT(max) > 2.2 V		2.8
V_OVPF0	Fixed OVP voltage threshold (VR12.0)	ENABLE is high and (V_VSP–V_VSN) > V_OVPH5 for 1 μs, PWM → LO,	1.7	1.75	1.8
V_OVPT5	Tracking OVP offset (VR12.5)	Measured at the VSP pin w/r/t VID code, device latches OFF	340	375	405	mV
V_OVPT0	Tracking OVP offset (VR12.0)	Measured at the VSP pin w/r/t VID code, device latches OFF	200	225	250	mV
V_RDYL	VR_RDY low (UVP) threshold	Measured at the VSP pin w/r/t VID code, device latches OFF	175	207	235	mV
t_RDYDGLTO	VR_RDY deglitch time	Time from VSP out of overvoltage threshold to VR_RDY low		1		µs
t_RDYDGLTU	VR_RDY deglitch time	Time from VSP out of undervoltage threshold to VR_RDY low, (ƒ_SW = 500 kHz)		32		µs
t_HICCUP	Hiccup delay after UVP and OCP			22		ms
TSEN PIN AND THERMAL SHUTDOWN: THERMAL VOLTAGE LEVELS
V_TSEN	Thermal voltage definition	T_J = 90°C		1.32		V
		T_J = 95°C		1.36
		T_J = 100°C		1.4
		T_J = 105°C		1.44
		T_J = 110°C		1.48
		T_J = 115°C		1.52
		T_J = 120°C		1.56
		T_J = 125°C		1.6
I_TSEN	TSEN current	Leakage current	–3		3	µA
OTP_THLD	Over temperature protection threshold	Based on the temperature measured on TSEN pin, default value		125		°C
OTP_HYS	Over temperature protection hysteresis			15		°C
PWM and SKIP-NVM OUTPUT: I/O VOLTAGE AND CURRENT°C
V_PWML	PWMx output low level	I_LOAD = -1 mA		0.15	0.3	V
V_PWMH	PWMx output high Level	I_LOAD = +1 mA	2.5			V
V_{SKIP-NVM_L}	SKIP-NVM output low Level	I_LOAD = –1 mA		0.15	0.3	V
V_{SKIP-NVM_H}	SKIP-NVM output high Level	I_LOAD = +1 mA	2.5			V
R_{P-S_UV}	PWMx//SKIP-NVM resistance⁽¹⁾	ENABLE = LOW, or UVLO	10			MΩ
DYNAMIC PHASE SHEDDING: THRESHOLDS
I_DPSTHL	Dynamic phase add/drop low threshold current	MFR_SPEC_15 [3] = 0b		N.A		A
I_DPSTHL	Dynamic phase add/drop low threshold current	MFR_SPEC_15 [3] = 1b		10% × 4 × I_OCLx		A
I_DPSTHH	Dynamic phase add/drop high threshold voltage	MFR_SPEC_15 [2:0] = 000b		15% × 4 × I_OCLx		A
		MFR_SPEC_15 [2:0] = 001b		20% × 4 × I_OCLx
		MFR_SPEC_15 [2:0] = 010b		25% × 4 × I_OCLx
		MFR_SPEC_15 [2:0] = 011b		30% × 4 × I_OCLx
		MFR_SPEC_15 [2:0] = 1xxb		35% × 4 × I_OCLx
I_DPSHYS	Dynamic phase add/drop high hysteresis voltage	Hysteresis		5% × 4 × I_OCLx		A
PROGRAMMABLE DROOP SETTING
DROOP	Droop percentage settings	MFR_SPEC_08 [7:0] = 00h		0		%
		MFR_SPEC_08 [7:0] = 01h		25
		MFR_SPEC_08 [7:0] = 02h		50
		MFR_SPEC_08 [7:0] = 03h		75
		MFR_SPEC_08 [7:0] = 04h (Default Setting)		100
		MFR_SPEC_08 [7:0] = 10h		80
		MFR_SPEC_08 [7:0] = 20h		85
		MFR_SPEC_08 [7:0] = 30h		90
		MFR_SPEC_08 [7:0] = 40h		95
		MFR_SPEC_08 [7:0] = 50h		105
		MFR_SPEC_08 [7:0] = 60h		110
		MFR_SPEC_08 [7:0] = 70h		115
		MFR_SPEC_08 [7:0] = 80h		120
		MFR_SPEC_08 [7:0] = 90h		125
		MFR_SPEC_08 [7:0] = A0h		150
SKIP-NVM PIN: PROGRAM MODE SETTING (NVM OR PINSTRAP)
PGRM	Program mode for the configurations	R_SKIP-NVM ≤ 20 kΩ		Pinstrap		Program Mode
PGRM	Program mode for the configurations	R_SKIP-NVM ≥ 100 kΩ		NVM		Program Mode
IMON PIN: CURRENT MONITOR
I_IMON4LK	0% IMAX level current output	4 phase, IMAX=80A, Σ i_L= 0 A, R_IMON=74.38kΩ	0		4	A
I_IMON4LO	20% IMAX level current output	4 phase, IMAX=80A, Σ i_L = 16 A, R_IMON=74.38kΩ	13	16	18.5	A
I_IMON4MID	100% IMAX level current output	4 phase, IMAX=80A, Σ i_L= 80 A, R_IMON=74.38kΩ	75	80	84	A
I_IMON4HI	125% IMAX level current output	4 phase, IMAX=80A, Σ i_L= 100 A, R_IMON=74.38kΩ	94	100	105	A
VOUT MEASUREMENT: READ_VOUT
M_VOUT(rng)	V_OUT measurement range		0.5		2.3	V
READ_VOUT accuracy		0.5 V ≤ V_OUT < 0.7 V, VR12.0 mode	-2		+2	VID
		0.7V ≤ V_OUT ≤ 1.0 V, VR12.0 mode	-1		+1
		1.0V < V_OUT ≤ 1.52 V, VR12.0 mode	-2		+2
		0.5 V ≤ V_OUT ≤ 2.3 V, VR12.5 mode	-1		+1
MFR_READ_VOUT accuracy		0.5 V ≤ V_OUT < 0.7 V, VR12.0 mode	-12.5		12.5	mV
		0.7V ≤ V_OUT ≤ 1.0 V, VR12.0 mode	-7.5		7.5
		1.0V < V_OUT ≤ 1.52 V, VR12.0 mode	-10		10
		0.5 V ≤ V_OUT ≤ 2.3 V, VR12.5 mode	-12.5		12.5

(1) Specified by design. Not production tested.

6.6 I/O Timing Requirements

			MIN	TYP	MAX	UNIT
t_STARTUP1	Startup time	V_BOOT> 0 V, no faults, time from V3R3 high to VOUT ramp, C_VREF = 1 µF			1.2	ms
t_STARTUP2	Startup time	V_BOOT> 0 V, no faults, time from V3R3 high until the controller responds to PMBus commands, C_VREF = 1 µF			1.5	ms
t_{RDY_POD}	VR_RDY power-on-delay time⁽¹⁾	DAC settled to VR_RDY going high		1		ms
t_{OFF_MIN}	Controller minimum OFF time⁽¹⁾	Fixed value	20	50	80	ns
t_{EN_RDY}	ENABLE low to VR_RDY low		20		100	ns
t_{RDY_VSP}	VR_RDY low to VSP change⁽¹⁾				100	ns

(1) Specified by design. Not production tested.

6.7 Switching Characteristics

T_A = 25°C. (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
F-IMAX PIN: FREQUENCY
f_SW	Switching frequency	V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 20 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0000b	270	300	330	kHz
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 24 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0001b	360	400	440
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 30 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0010b	450	500	550
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 39 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0011b	540	600	660
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 56 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0100b	630	700	770
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 75 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0101b	720	800	880
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 100 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0110b	810	900	990
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 150 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0111b	900	1000	1100
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 20 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1000b	315	350	385
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 24 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1001b	405	450	495
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 30 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1010b	495	550	605
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 39 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1011b	585	650	715
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 56 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1100b	675	750	825
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 75 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1101b	765	850	935
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 100 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1110b	855	950	1045
		V_VIN = 12 V, V_VSP = 1.7 V R_F-IMAX = 150kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1111b	900	1000	1100

6.8 Typical Characteristics

Figure 1. VIN Supply Current vs Junction Temperature

V_UVLO = 7.25 V

Figure 3. VIN UVLO Voltage vs Junction Temperature

Figure 5. Reference Voltage vs Junction Temperature

Figure 2. V5 Supply Current vs Junction Temperature

Figure 4. V5 UVLO Voltage vs Junction Temperature

I_LOAD = 5 mA

Figure 6. V3R3 Load Regulation vs Junction Temperature