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ADC3660 16-Bit, 0.5 to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
SBASA01B
September 2020 – March 2022
ADC3660
PRODUCTION DATA
CONTENTS
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ADC3660 16-Bit, 0.5 to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - Power Consumption
6.6
Electrical Characteristics - DC Specifications
6.7
Electrical Characteristics - AC Specifications
6.8
Timing Requirements
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Input
8.3.1.1
Analog Input Bandwidth
8.3.1.2
Analog Front End Design
8.3.1.2.1
Sampling Glitch Filter Design
8.3.1.2.2
Analog Input Termination and DC Bias
8.3.1.2.2.1
AC-Coupling
8.3.1.2.2.2
DC-Coupling
8.3.1.3
Auto-Zero Feature
8.3.2
Clock Input
8.3.2.1
Single Ended vs Differential Clock Input
8.3.2.2
Signal Acquisition Time Adjust
8.3.3
Voltage Reference
8.3.3.1
Internal voltage reference
8.3.3.2
External voltage reference (VREF)
8.3.3.3
External voltage reference with internal buffer (REFBUF)
8.3.4
Digital Down Converter
8.3.4.1
DDC MUX
8.3.4.2
Digital Filter Operation
8.3.4.2.1
FS/4 Mixing with Real Output
8.3.4.3
Numerically Controlled Oscillator (NCO) and Digital Mixer
8.3.4.4
Decimation Filter
8.3.4.5
SYNC
8.3.4.6
Output Formatting with Decimation
8.3.5
Digital Interface
8.3.5.1
SDR Output Clocking
8.3.5.2
Output Data Format
8.3.5.3
Output Formatter
8.3.5.4
Output Bit Mapper
8.3.5.5
Output Interface/Mode Configuration
8.3.5.5.1
Configuration Example
8.3.6
Test Pattern
8.4
Device Functional Modes
8.4.1
Normal Operation
8.4.2
Power Down Options
8.4.3
Digital Channel Averaging
8.5
Programming
8.5.1
Configuration using PINs only
8.5.2
Configuration using the SPI interface
8.5.2.1
Register Write
8.5.2.2
Register Read
8.6
Register Maps
8.6.1
Detailed Register Description
9
Application and Implementation
9.1
Typical Application
9.1.1
Design Requirements
9.1.2
Detailed Design Procedure
9.1.2.1
Input Signal Path
9.1.2.2
Sampling Clock
9.1.2.3
Voltage Reference
9.1.3
Application Curves
9.2
Initialization Set Up
9.2.1
Register Initialization During Operation
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Support Resources
12.2
Trademarks
12.3
Electrostatic Discharge Caution
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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DATA SHEET
ADC3660 16-Bit, 0.5 to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
1
Features
Dual channel
16-bit 65 MSPS ADC (max output rate = 31 Msps)
Noise floor: –159 dBFS/Hz
Ultra-low power: 71 mW/ch at 65 MSPS
16-Bit, no missing codes
INL: ±2 LSB; DNL: ±0.2 LSB
Reference: external or internal
Input bandwidth: 900 MHz (3 dB)
Industrial temperature range: –40°C to +105°C
On-chip digital down converter
Decimation by 2, 4, 8, 16, 32
32-bit NCO
Serial CMOS interface
Single 1.8-V supply
Small footprint: 40-WQFN (5 mm × 5 mm) package
Spectral performance (f
IN
= 5 MHz):
SNR: 81.9 dBFS
SFDR: 88 dBc HD2, HD3
SFDR: 102 dBFS worst spur