Design Goals
Input |
Output |
Supply |
ViMin |
ViMax |
VoMin |
VoMax |
Vcc |
Vee |
Vref |
–10V |
10V |
–10V |
10V |
15V |
–15V |
0V |
Design Description
This circuit controls the slew rate of
an analog gain stage. This circuit is intended for symmetrical slew rate
applications. The desired slew rate must be slower than that of the op amp chosen to
implement the slew rate limiter.
Design Notes
- The gain stage op-amp and slew rate
limiting op amp should both be checked for stability.
- Verify that the current demands for
charging or discharging C1 plus any load current out of U2
will not limit the voltage swing of U2.
Design Steps
- Set slew rate and choose a standard
value for the feedback capacitor, C1.
- Choose the value of R2
to set the capacitor current necessary for the desired slew rate.
- Compensate feedback network for
stability. R1 adds a pole to the 1/β network. This pole should be
placed so that the 1/β curve levels off a decade before it intersects the open
loop gain curve (200 Hz, for this example).
Design Simulations
Transient Simulation
Results
Design Featured Op Amp
OPA192 |
Vcc
|
4.5V to 36V |
VinCM
|
Rail-to-rail |
Vout
|
Rail-to-rail |
Vos
|
5µV |
Iq
|
1mA/Ch |
Ib
|
5pA |
UGBW |
10MHz |
SR |
20V/µs |
#Channels |
1, 2, and 4 |
OPA192 |
Design
Alternate Op Amp
TLV2372 |
Vcc
|
2.7V to 16V |
VinCM
|
Rail-to-rail |
Vout
|
Rail-to-rail |
Vos
|
2mV |
Iq
|
750µA/Ch |
Ib
|
1pA |
UGBW |
3MHz |
SR |
2.1V/µs |
#Channels |
1, 2, and 4 |
TLV2372 |