Design Goals

Design Description

The vast majority of electronic circuits operate from one or more positive supply voltages, which is why there are many more positive voltage regulators on the market than negative ones. The dearth of negative voltage regulators is even more pronounced in the space market, where there is a very limited number of such devices. There are times, however, when a particular device or application circuit requires a negative voltage regulator.

Note that the feedback network is connected to the non-inverting input of the op-amp because of the signal inversion caused by Q1.

Design Notes

The power dissipation and junction temperature in pass transistor Q1 must not exceed the maximum values allowed by the device and by your application. In space applications, the maximum allowed power dissipation in a transistor may be significantly less than the rating of the device. For example, the European Space Agency (ESA) recommends a derating factor of 65%. Similarly, although Q1 is specified with a maximum junction temperature of 200°C, ESA recommends a junction temperature not greater than 110°C. In applications with a large voltage drop across the negative regulator, the power dissipation in Q1 might exceed the maximum allowed. However, in such applications there no need for an LDO regulator and a standard type with larger dropout such as the LM137QML-SP can be used.

The op-amp used in this circuit must have an output stage capable of operating close to the negative supply rail of the op amp. The LM158QML-SP was chosen for this circuit because it meets this criterion, has a long space heritage, and withstands a total ionizing dose up to 100 krad (Si). Other op amps can be used, but the feedback stabilization may need to be adjusted to suit the frequency response of the op amp.

Design Steps

• Choose R2 so that the current flowing through the feedback network is approximately 1 mA.
  
  
  
• Choose R3 to set the output voltage to the desired value.
  
  
  
• Choose a product of output capacitance C_O and equivalent series resistance R_ESR to generate a zero below 10 kHz (lower is generally better). The frequency of the ESR zero is given by:
  
  
  

  R_ESR can be either inherent in the capacitor used or included separately in series with a low-ESR capacitor (as it was in this case).

• An optional feedforward capacitor C_FF across the feedback network provides an additional zero that improves transient response. The value of C_FF is best selected experimentally. Note that C_FF cannot be used on its own to stabilize the loop. This is because the pole and the zero formed by R2, R3, and C_FF are too close to each other in the frequency domain to stabilize the loop over the whole range of output currents.
• An additional capacitor, C1, reduces the initial voltage step response caused by the relatively high value of
  R_ESR. The value of C1 is low compared to C_O and does not significantly affect stability.

Design Simulations

DC Simulation Results

Load Regulation

The following plot shows the output voltage variation as the output current varies from 0 mA to 100 mA.

Line Regulation

The following plot shows the output voltage variation as the negative supply voltage varies from –4 V to –2 V.

AC Simulation Results

Stability

The following plot shows the frequency response of the circuit with an output current of 10 mA.

The following plot shows the frequency response of the circuit with an output current of 100 mA.

Ripple Rejection

The following plot shows the simulated ripple rejection of the circuit.

Transient Simulation Results

Load Transient Response

The following scope plot shows the transient response of the circuit to a 10-mA to 90-mA load step.

Design References

Texas Instruments, AN-1482 LDO Regulator Stability Using Ceramic Output Capacitors Application Report

Design Featured Op Amp