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User Guide for Powering JacintoTM 7 J7200 DRA821 with Single TPS6594-Q1 PMIC, PDN-2A
SLVUCD4
November 2022
DRA821U
,
DRA821U-Q1
,
TPS6594-Q1
CONTENTS
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User Guide for Powering JacintoTM 7 J7200 DRA821 with Single TPS6594-Q1 PMIC, PDN-2A
PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
Trademarks
1
Introduction
2
Device Versions
3
Processor Connections
3.1
Power Mapping
3.2
Control Mapping
4
Supporting Functional Safety Systems
4.1
Achieving ASIL-B System Requirements
4.2
Achieving up to ASIL-D System Requirements
5
Static NVM Settings
5.1
Application-Based Configuration Settings
5.2
Device Identification Settings
5.3
BUCK Settings
5.4
LDO Settings
5.5
VCCA Settings
5.6
GPIO Settings
5.7
Finite State Machine (FSM) Settings
5.8
Interrupt Settings
5.9
POWERGOOD Settings
5.10
Miscellaneous Settings
5.11
Interface Settings
5.12
Watchdog Settings
6
Pre-Configurable Finite State Machine (PFSM) Settings
6.1
Configured States
6.2
PFSM Triggers
6.3
Power Sequences
6.3.1
TO_SAFE_SEVERE and TO_SAFE
6.3.2
TO_SAFE_ORDERLY and TO_STANDBY
6.3.3
ACTIVE_TO_WARM
6.3.4
TO_ACTIVE
6.3.5
TO_RETENTION
7
Application Examples
7.1
Moving Between States: ACTIVE and RETENTION
7.1.1
ACTIVE
7.1.2
RETENTION
7.2
Entering and Exiting Standby
7.3
Entering and Existing LP_STANDBY
7.4
GPIO8 and Watchdog
8
References
IMPORTANT NOTICE
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