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AM263x is a system on chip (SoC) with Arm® Cortex®-R5F clusters and a dedicated accelerator for real time control. The clusters can be configured as either dual core mode or lockstep mode. And, the accelerator is named as control subsystem and includes interface modules like ADC, DAC, and PWM. This work takes core 0-0 as an example and demonstrates features of one R5F core and a group of interface modules for one traction inverter. This section gives a brief introduction on the R5F cluster and the control sub-system. More details on the SoC can be found in the AM263x Sitara™ Microcontrollers Data Sheet and the AM263x Sitara Processors Technical Reference Manual. Details on inverter hardware can be found in the ASIL D Safety Concept-Assessed High-Speed Traction, Bi-directional DC/DC Conversion Reference Design.
The Arm® Cortex®-R5F cluster includes two R5F cores accompanying memories like L1 cache and tightly-coupled memories (TCM), standard Arm CoreSight™ debug and trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules for protocol conversion and address translation for easy integration into the SoC. More detailed block diagram can be found in AM263x technical reference manual. The key to solve real time control problem is to understand the impacts from cache and TCM. Instructions and data can be allocated to either On-Chip RAM or TCM by link command file when program is built. During execution, frequently used instructions and data in On-Chip RAM will be taken into cache automatically. As a result, execution time is significantly improved. But, the data in On-Chip RAM is not updated until it is written back from cache. When data is in cache, the only way to access is via instructions running in the core and memory view from integrated development environment (IDE) like Code Composer Studio™ (CCS) is not able to read cache. However, there is a way to read cache with CCS via a section of program operating universal asynchronous receiver/transmitter (UART) inside the core. Details on the UART method will be introduced in a following section. On the other hand, instructions and data allocated to TCM are kept at the address and available to memory view all the time. Generally, execution time of program in cache and TCM is very close but that of program in On-Chip RAM is much slower. And, the operation transferring program from On-Chip RAM to cache takes some time and introduces some non-predictive latency. If the latency is significant to the requirement from application, it is highly encouraged to store the application program in TCM. Details on TCM address can be found in AM263x technical reference manual. In this work, the interrupt program for field oriented control and software resolver to digital converter are located in TCM. The link command file is available as an example in CCS project folder.
The accelerator for real time control inherits Texas Instrument’s classic C2000 control modules widely used around the world. It includes Analog-to-Digital Converter (ADC), Analog Comparator, Buffered Digital-to-Analog Converter, Enhanced Pulse Width Modulator (EPWM), Enhanced Capture, Enhanced Quadrature Encoder Pulse, Fast Serial Interface, Sigma Delta Filter Module, and Crossbar. Details on the modules are available in AM263x technical reference manual. With the help of an intuitive system configuration tool, SYSCONFIG, it is also possible to configure those modules with reduced exposure to implementation details. Details on SYSCONFIG can be found in AM263x Software Development Kit (SDK). The key for module synchronization is to configure PWM synchronization input/output in EPWM Time Base section and ADC Start-of-Conversion (SOC) trigger in EPWM Event-Trigger section. Time Base is to align multiple PWM channels while Event-Trigger is to synchronize features like ADC, DMA and Interrupt. One example for traction inverter is located in CCS project folder of traction inverter demo. In the example, one PWM channel is set to trigger updates for resolver excitation signal via DMA and DAC at higher frequency, and three PWM channels are used to create inverter signal and generate ADC SOC. In this way, resolver excitation signal from DAC is aligned to the desired phase for ADC samples. Multiple ADC units can share the same SOC. In other words, multiple samples can be taken simultaneously across multiple ADC units. Within one ADC unit, the sequence of samples can be configured in SOC Configuration section. And, ADC interrupt can be set in INT Configuration. The interrupt can be triggered at either the start of one ADC conversion or the end of one ADC conversion. Some simple examples on PWM and ADC are available in AM263x SDK under "\examples\drivers\epwm" and "\examples\drivers\adc". More details on the APIs can be found in AM263x SDK under "\source\drivers". The header files have great details in comments.
As we mentioned, there are some topics to be considered in development, like SoC architecture and SDK APIs. More details on those can be found in AM263x technical reference manual and SDK package. In the following sections, this work is going to focus on how to use the example project as a framework to accelerate development of traction inverter, and how to migrate existing project code to AM263x.
The framework includes the resources highlighted in Figure 1-1 and is built into the traction system in Figure 1-2. TIDM-02009 is the traction inverter reference design hardware. It includes a power model, gate drivers, current and voltage samples, resolver analog front end, and some connection interfaces. The motor includes a resolver taking sine wave excitation and sending modulated feedbacks for position sensing. Field Oriented Control is implemented with Cluster-0 Core-0. The real-time control section in ADC INT1 is allocated to TCM for the most deterministic execution time.
For AM263x, real time debug is enabled by UART connection between CCS and AM263x. With real time debug, global variables can be added to expression window and ready for read/write during continuous run of the program. The connection is built by debug program in the listed files.
Even though there are four files listed here, there is only two functions required in application program. One is "SerialCmd_init()" called in initialization and the other is "SerialCmd_read()" called in background loop of BareMetal or low priority task of RTOS. This section focus on how to create the UART connection and how to launch real time debug in CCS.
It is recommended to check the following CCS driver file if the CCS version is older than 11.1. The configuration of Cortex_R5 should be similar to Figure 2-1. If any line is missing, it is necessary to add the line showing in Figure 2-1. As for content of the lines, COM Port and Baud Rate need to be updated in target configuration file, which is included in the next step.
For a control card in Figure 2-2, it offers both JTAG and UART ports in one USB port. Details on hardware connection can be found in AM263x Control Card User's Guide. It is necessary to create a target configuration file for the debug ports. A step-to-step guide is given in screen shots from Figure 2-3 to Figure 2-10. Briefly, a target configuration file is created and then configured with both JTAG and UART. The UART COM Port in Figure 2-10 should match PC Device Manager COM Port for JTAG probe Application/User UART. The Baud Rate in Figure 2-10 should be consistent with SoC UART Baud Rate configured in next step.
There are multiple ways to use UART0 as a debug interface. They are Debug Log and Serial Command Monitor. Debug Log is a built-in tool located at Driver Porting Layer of SDK. Like Serial Cmd Monitor, its function must be located out of interrupt callback. It is a handy tool enabling string input and output. But, input and output go through UART console only. There is no built-in GUI like Expression Window and Graph in CCS. It is recommended to disable UART0 in Debug Log at Figure 2-11 and configure UART0 instance for Serial Command Monitor at Figure 2-12. As the name of UART in Sysconfig, "CONFIG_UART_CONSOLE", matches the handle name in "Serial_Cmd_HAL.c", it not necessary to modify the two functions required by initialization and background loop. They can be simply inserted as Figure 2-13.
After building the program, debug window should be opened with the target configuration file created in Section 2.1.2. If the created target configuration file is not already opened, it can be located by following Figure 2-14 and looking into "User Defined" folder of the "Target Configuration" window. The created target configuration file should be under folder named as "User Defined". After right click on the file, a menu shows up and there is a option "Launch Selected Configuration" as shown in Figure 2-15. Then, debug window shows up. The steps to connect target, load image and run via JTAG can be found in many CCS tutorials. The processor must be running continuously before connecting to UART. As the UART connection is based on continuous operation of the program, UART connection will be broken and CCS will be frozen by Break-point, Suspend, Terminate or any other events stopping the Serial Command Monitor program from running. Sometimes, it is just a habit to use those features when they are available. It is recommended to disconnect target via JTAG as shown in Figure 2-16 while using UART connection. When the processor is running, UART connection can be established by simply select the UART connection → Run → Load → Load Symbols as shown in Figure 2-17.
Sysconfig is a GUI-based configuration tool. It significantly simplifies the configuration of control peripherals and interrupts. The items inside Sysconfig are described in a very intuitive way. After the configuration is completed in Sysconfig, configuration program will be automatically generated and connected to main function during build. They are stored under the following files under a folder named "Generated Source". It is worth attention that the content of those files will be refreshed after a build with Sysconfig. It is fine to copy program from these files and reuse in other parts of the application program. More details on Sysconfig can be found from SDK documents. In the following parts of this section, the focus is on how to setup control peripherals and interrupt for a traction inverter.
The PWM module of AM263x inherited features from TI classic C28 controllers. With a unique XBAR architecture of AM263x, its ADC SOC triggers are able to trigger not only ADC events but also various of other events like DMA. This part will give some details on how to synchronize PWM modules and how to configure PWM modules to trigger ADC and DMA. More details can be found in Technical Reference Manual.
Figure 2-18 presents a summary of ePWM7, which is used to trigger DMA for resolver excitation signal updating at 200 kHz via DAC. There are couple tabs available for configuration. But, for the DMA trigger purpose, there are only three tabs to be updated.
Figure 2-19 shows details on Time Base. EPWM7 is configured as 200 kHz, Up-Count, and following Sync Out Pulse from ePWM0. It is worth attention that peripherals are operated at 200 MHz while R5F cores are running at 400 MHz.
Figure 2-20 shows details on Event Trigger. The key contents are listed below. ePWM7 is to generate two triggers, ADC SOCA and SOCB. The two triggers are from different source events The one related to CMPA is configured in the Counter Compare tab as shown in Figure 2-21.
EPWM0 is used as Phase A of traction inverter. All EPWM channels are synchronized to EPWM0. It is configured as 10 kHz, Up-Down Count, No Sync In, Sync Out and ADC SOC trigger at counter zero as shown by Figure 2-22 and Figure 2-23.
Dead-Band of EPWM0 is configured as Figure 2-24. Delay value of 200 indicates 1000 ns because of the 200 MHz peripherals clock.
ADC4 is taken as a example in this part. Figure 2-25 gives a summary of ADC4. It is similar to TI classic C28 controllers.
Figure 2-26 gives an example on SOC0. There are 16 SOC for every ADC. The ADC channel can be configured as either single end or differential. Here, it is triggered by a PWM SOC event.
Once the Start Of Conversions are configured, INTs can be updated like shown in Figure 2-27. The INT is to be created at the End Of Conversion for SOC5.
In Figure 2-28, ADC INT is connected to INT_XBAR_0 via XBAR system. The XBAR name is the one used in interrupt registration in later sections.