The features and characteristics of any AM263x IP are identified by the part number. Table 2-1 describes how to decrypt features. See the data sheet to get the details of speed, memory, number of Control IPs, networking settings, and so on. Table 2-2 is classified according to the part number as explained in Table 2-1.

Table 2-2 specifies differences between six part numbers. More information regarding these differences is available in the Device Comparison section of AM263x Sitara™ Microcontrollers, data sheet.

In AM263x multiple R5F cores are arranged in cluster with 256KB of shared tightly coupled memory (TCM) as shown in Figure 3-1.

Figure 3-1 R5 cores and TCM in AM263x Family

Here after in this document the R5 cores are defined as explained below based on the position of the core in the cluster:

AM2634 has two R5 clusters:

• The first cluster is called R50.
  • The first core in the first cluster is called core R50-0.
  • The second core in first cluster is called core R50-1.

• The second cluster is called R51.
  • The first core in the second cluster is called R51-0.
  • The second core in the second cluster is called R51-1.

AM2632 has two R5 clusters:

• The first cluster is called R50.
  • The first core in the first cluster is called core R50-0.
• The second cluster is called R51.
  • The first core in the second cluster is called R51-0.

Am2631 has one R5 cluster:

• The single cluster is called R50.
  • The first core in this cluster is called core R50-0

All the examples in the SDK are supported for AM2634 devices. Currently, IPC and Networking are not supported for some devices. The 8th character of the part numbers in Section 2 represent Device Operating Performance Points of the device. Similarly, the 6th character represents number of R5 cores in the device, see Section 2 for more information. For example in AM2632COLFHAZCZR, O is the speed and memory setting and 2 represents two R5 cores. Section 4 lists supported examples in the MCU PLUS SDK for AM263x family of devices, based on the memory setting and number of cores.

Changes in the IPC Notify Example to build through CCS to create a dual core .appimage for AM2632:

This section contains changes made in the IPC Notify example to create a Dual Lockstep Core (two cores) example from an existing four-core IPC Notify example.

This section provides a simple method to create a Dual Lockstep Core (two cores) example from an existing four-core IPC Notify example. This example does not involve any system project; therefore, the user must use the command line to create a final combined app image. Steps for creating a Dual Core Appimage are described below.

• Import IPC Notify example for R50-0 and R51-0 (see also Section 3.1) from the SDK as shown below. Ignore the system project.

Figure 5-1 IPC Notify Example for R50-0 and R51-0

• Modify your example.syscfg to support the IPC notify feature to the cores 0-0 and 1-0. Subsequently, disable IPC Notify feature for cores 1-0 and 1-1.

Figure 5-2 IPC Notify R50_0 Syscfg

Figure 5-3 IPC Notify R51_0 Syscfg

• Change the Remote Core ID list to support only core 1-0, and remove remaining cores as shown below. Make this change in ipc_notify_echo .c file of both ipc_notify_echo_am263x-cc_r5fss0-0_nortos_ti-arm-clang and ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang projects.

uint32_t gRemoteCoreId[] = {
    CSL_CORE_ID_R5FSS1_0, 
    CSL_CORE_ID_MAX 
};

• Build these projects individually. After building, .rprc files are available for both the projects.
• Combine these .rprc to form a dual-core .appimage using the following command.

C:\ti{sysconfig}\nodejs\node C:\ti{mcu_plus_sdk}/tools/boot/multicoreImageGen/multicoreImageGen.js --devID 55 --out Debug/Combined.debug.appimage ../ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang/Debug/ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang.rprc@0 ../ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang/Debug/ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang.rprc@2

The command format for MulticoreImage Generation is given below.

cd ${SDK_INSTALL_PATH}/tools/boot/multicoreImageGen${NODE} multicoreImageGen.js --devID {DEV_ID} --out {Output image file (.appimage)} {core 1 rprc file}@{core 1 id} [ {core n rprc file}@{core n id} ... ]

This process helps to import the existing IPC Notify example as a 2-core system project with R50_0 as the main core and R51_0 as the remote core. The following changes need to be done in the make files in the SDK for IPC Notify. Choose the folder depending on your device type CC or LP.

Open the system_freertos_nortos makefile at the locaion:examples\drivers\ipc\ipc_notify_echo\am263x-cc\system_freertos_nortos\ makefile.

• Retain the CORE_0 definition. Remove CORE_1 and CORE_2 definitions from lines 18 and 19 as these are not required.

• Define CORE_1 as below:

CORE_1=--script ../r5fss1-0_nortos/example.syscfg --context r5fss1-0 --output ../r5fss1-0_nort os/ti-arm-clang/generated

• Remove $(CORE_3) and $(CORE_2) from CORES. And define CORES as shown.

CORES = \
$(CORE_1) \
$(CORE_0) \

• Remove r5fss0-1 and r5fss1-1 instances from all: syscfg section.

all: 
syscfg $(MAKE) -C ../r5fss0-0_freertos/ti-arm-clang/ all
$(MAKE) -C ../r5fss1-0_nortos/ti-arm-clang/ all 
$(MAKE) $(MULTI_CORE_BOOTIMAGE_NAME)

• Remove r5fss0-1 and r5fss1-1 instances from clean section.

clean: 
$(MAKE) -C ../r5fss0-0_freertos/ti-arm-clang/ clean
$(MAKE) -C ../r5fss1-0_nortos/ti-arm-clang/ clean 
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME) 
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME_SIGNED) 
$(RM) $(MULTI_CORE_BOOTIMAGE_NAME_XIP)

• Remove r5fss0-1 and r5fss1-1 instances from scrub section.

scrub: 
$(MAKE) -C ../r5fss0-0_freertos/ti-arm-clang/ scrub 
$(MAKE) -C ../r5fss1-0_nortos/ti-arm-clang/ scrub

• Remove r5fss0-1 and r5fss1-1 instances from MULTI_CORE_APP_PARAMS section.

MULTI_CORE_APP_PARAMS = \

../r5fss0-0_freertos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

 ../r5fss1-0_nortos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc@$(BOOTIMAGE_CORE_ID_r5fss1-0) \

• Remove r5fss0-1 and r5fss1-1 instances from MULTI_CORE_APP_PARAMS_XIP section.

MULTI_CORE_APP_PARAMS_XIP = \

 ../r5fss0-0_freertos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc_xip@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

 ../r5fss1-0_nortos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc_xip@$(BOOTIMAGE_CORE_ID_r5fss1-0) \

• Remove r5fss0-1 and r5fss1-1 instances from MULTI_CORE_BOOTIMAGE_DEPENDENCY section.

MULTI_CORE_BOOTIMAGE_DEPENDENCY = \
 ../r5fss0-0_freertos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc \
../r5fss1-0_nortos/ti-arm-clang/ipc_notify_echo.$(PROFILE).rprc \

Open the projectspec makefile at the location: examples\drivers\ipc\ipc_notify_echo\am263x-cc\system_freertos_nortos\ makefile_projectspec.

Make the following changes in this makefile:

• Remove r5fss0-1 and r5fss1-1 instances from clean section to support only r5fss0-0 and r5fss1-0.

clean:
$(CCS_ECLIPSE) -noSplash -data $(MCU_PLUS_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects
$(PROJECT_NAME) -ccs.configuration
$(PROFILE) -ccs.clean
$(MAKE) -C ../r5fss0-0_freertos/ti-arm-clang/ -f makefile_projectspec clean
$(MAKE) -C ../r5fss1-0_nortos/ti-arm-clang/ -f makefile_projectspec clean

Open the bootimage_gen makefile at the location: examples\drivers\ipc\ipc_notify_echo\am263x-cc\system_freertos_nortos\ makefile_system_ccs_bootimage_gen.

Make the following changes in this makefile:

• Remove r5fss0-1 and r5fss1-1 instances from MULTI_CORE_APP_PARAMS section.

MULTI_CORE_APP_PARAMS = \
../ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang/$(PROFILE)/ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang.rprc@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
../ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang/$(PROFILE)/ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang.rprc@$(BOOTIMAGE_CORE_ID_r5fss1-0) \

• Remove r5fss0-1 and r5fss1-1 instances from MULTI_CORE_APP_PARAMS_XIP section.

MULTI_CORE_APP_PARAMS_XIP = \
 ../ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang/$(PROFILE)/ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang.rprc_xip@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
../ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang/$(PROFILE)/ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang.rprc_xip@$(BOOTIMAGE_CORE_ID_r5fss1-0) \

Open the system projectspec file at the location: examples\drivers\ipc\ipc_notify_echo\am263x-cc\system_freertos_nortos\ system.projectspec.

Make the following changes in thisprojectspec file:

• Remove r5fss0-1 and r5fss1-1 projectspec files from getting imported with the system_freertos_nortos project (lines 4 and 6).

<projectSpec>
<import spec="../r5fss0-0_freertos/ti-arm-clang/example.projectspec"/>
<import spec="../r5fss1-0_nortos/ti-arm-clang/example.projectspec"/>

Open the system projectspec file at the location: examples\drivers\ipc\ipc_notify_echo\am263x-cc\system_freertos_nortos\ system.xml.

Make the following changes in this projectspec file:

• Remove r5fss0-1 and r5fss1-1 cores project configurations from the xml file and only keep 0-0 and 1-0 cores. Modify core 1 as r5fss1-0 core as shown below.

<project configuration="@match" id="project_0" name="ipc_notify_echo_am263x-cc_r5fss0-0_freertos_ti-arm-clang">
</project>
<core id="MAIN_PULSAR_Cortex_R5_0_0" project="project_0"/>
<project configuration="@match" id="project_1" name="ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang">
</project>
<core id="MAIN_PULSAR_Cortex_R5_1_0" project="project_1"/>

After modifying the system project make files, import this example into your CCS. This step is the same as the other system projects.

Figure 5-4 Importing Dual-Core System Project for IPC Notify

Modify your example.syscfg to support IPC notify feature to the cores 0-0 and 1-0. Subsequently, disable IPC Notify feature for cores 1-0 and 1-1.

Figure 5-5 IPC Notify R50_0 Syscfg

Figure 5-6 IPC Notify R50_0 Syscfg

Change the Remote Core ID List to support only core 1-0, and remove rest of the cores as shown below. Make this change in ipc_notify_echo .c file of both ipc_notify_echo_am263x-cc_r5fss0-0_nortos_ti-arm-clang and ipc_notify_echo_am263x-cc_r5fss1-0_nortos_ti-arm-clang projects.

uint32_t gRemoteCoreId[] = {
    CSL_CORE_ID_R5FSS1_0, 
    CSL_CORE_ID_MAX 
};

Figure 5-7 Appimage Generated for Dual-Core Project

In MCU-PLUS-SDK_AM263x, system projects are configured for 2-core devices by default. But the examples are present for core - R50_0 and R50_1. These examples can be modified to enable the system project for the cores R50_0 and R51_0.

To find the system projects, go to → C:\ti\mcu_plus_sdk_am263x_08_05_00_24\examples\empty. Here, the SDK has 2 System Projects: freeRtos System Project and Nortos System Project. The engineer can choose a system project for the application.

The following files need to be modified:

1. examples\empty\am263x-cc\system_nortos\makefile

2. examples\empty\am263x-cc\system_nortos\makefile_projectspec

3. examples\empty\am263x-cc\system_nortos\makefile_system_ccs_bootimage_gen

4. examples\empty\am263x-cc\system_nortos\system.projectspec

5. examples\empty\am263x-cc\system_nortos\system.xml

Replace r5fss0-1 core with r5fss1-0 in these files. These changes are explained in the Section 5.