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  • LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

    • SNLS508 September   2015 LMH0318

      PRODUCTION DATA.  

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  • LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Loss of Signal Detector
      2. 8.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 8.3.3 2:1 Multiplexer
      4. 8.3.4 Clock and Data Recovery
      5. 8.3.5 Eye Opening Monitor (EOM)
      6. 8.3.6 Fast EOM
        1. 8.3.6.1 SMBus Fast EOM Operation
        2. 8.3.6.2 SPI Fast EOM Operation
      7. 8.3.7 LMH0318 Device Configuration
        1. 8.3.7.1 MODE_SEL
        2. 8.3.7.2 ENABLE
        3. 8.3.7.3 LOS_INT_N
        4. 8.3.7.4 LOCK
        5. 8.3.7.5 SMBus MODE
        6. 8.3.7.6 SMBus READ/WRITE Transaction
        7. 8.3.7.7 SPI Mode
          1. 8.3.7.7.1 SPI READ/WRITE Transaction
          2. 8.3.7.7.2 SPI Write Transaction Format
          3. 8.3.7.7.3 SPI Read Transaction Format
        8. 8.3.7.8 SPI Daisy Chain
          1. 8.3.7.8.1 SPI Daisy Chain Write Example
          2. 8.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 8.3.8 Power-On Reset
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Register Maps
      2. 8.5.2 Global Registers
      3. 8.5.3 Receiver Registers
      4. 8.5.4 CDR Registers
      5. 8.5.5 Transmitter Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for All Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Solder Profile
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTW|24
    • MPQF167C
Thermal pad, mechanical data (Package|Pins)
  • RTW|24
    • QFND450A
Orderable Information
  • snls508_oa
  • snls508_pm
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  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

1 Features

  • Supports ST 424(3G), 292(HD), 259(SD), MADI, and DVB-ASI
  • Locks to rates 2.97 Gbps, 1.485 Gbps, or Divided by 1.001 sub-rates, and DVB-ASI
  • Reference-free Operation with Fast Lock Time covering all Supported or Selected Data Rates
  • 75 Ω and 100 Ω Transmitter Outputs
  • Integrated 2:1 Mux Input, 1:2 Demux/Fanout Outputs
  • Automatic Slew Rate Based on Input Rate Detect
  • On-chip Eye Monitor
  • Low 300 mW Power Consumption With Automatic Power Down On Loss Of Input Signal
  • Programmable via SPI, Or SMBus Interface
  • Single 2.5 V Supply Operation
  • Small 4 mm × 4 mm 24-pin QFN Package
  • -40°C to +85°C Operating Temperature Range
  • Footprint compatible with LMH1218 for easy upgrade to 12G

2 Applications

  • SMPTE Compatible Serial Digital Interface (SDI)
  • Broadcast Video Routers, Switches, and Monitors
  • Digital Video Processing and Editing
  • DVB-ASI and Distribution Amplifiers

3 Description

The LMH0318 is a 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver designed to drive serial video data compatible to SMPTE-SDI and DVB-ASI standards. The clock and data recovery circuit eliminates accumulated jitter and detects the incoming data rate without requiring an external reference clock. The integrated driver with 75 ohm and 50 ohm outputs enables multiple media options such as coax and FR4 PCB.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH0318 WQFN (24) 4 mm × 4 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified SPI Schematic

LMH0318 3900252.gif

4 Revision History

DATE REVISION NOTES
September 2015 * Initial release.

5 Description continued

The integrated 2-to-1 MUX on the input of the LMH0318 enables selection between two video sources, while the programmable equalizer compensates for the PC board loss to extend signal reach. With a wide range clock-and-data recovery (CDR) circuit, the on-chip reclocker automatically detects and locks to serial data from 270 Mbps to 2.97 Gbps without the need for an external reference clock and loop filter component, thereby simplifying board design and lowering system cost. The reclocked serial data can be routed to either the 75 Ω or 50 Ω transmitter output, or both simultaneously (1-to-2 fanout mode). The output voltage swing is compatible to ST 424, 344, 292, and 259 standards.

A non-disruptive eye monitor allows for real-time measurement of serial data to simplify system startup or field tuning. The LMH0318 is pin compatible with the LMH1218, 12 Gbps Cable Driver with Integrated Reclocker.

6 Pin Configuration and Functions

24-Pin WQFN
Package RTWA0024A
(Top View)
LMH0318 3908009.gif

Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD

PIN I/O DESCRIPTION
NAME NO.
CONTROL/INDICATOR I/O
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
  • SPI mode. See Initialization Set Up
SS_N 2 Input, 2-Level SPI Slave Select. . This pin has internal pull up
SCK 3 Input, 2.5V LVCMOS, 2-Level SPI serial clock input
MOSI 4 Input, 2-Level SPI Master Output / Slave Input. LMH0318 SPI data receive
RESERVED 5,14,17,
18		 No Connect
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default):
  • Reserved

20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOS_INT_N 13 Output,
LVCMOS Open Drain, 2-Level		 Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pull-up resistor is required. This pin is 3.3 V LVCMOS tolerant.
MISO 15 Output, 2.5 V LVCMOS, 2-Level SPI Master Input / Slave Output. LMH0318 SPI data transmit
LOCK 16 Output, 2.5V LVCMOS, 2-Level Indicates CDR lock detect status
High:
  • CDR locked

Low:
  • CDR not locked
HIGH SPEED DIFFERENTIAL I/O
IN0+ 11 Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors.
IN0- 12 Input, Analog
IN1+ 8 Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7 µF AC coupling capacitors.
IN1- 9 Input, Analog
OUT0+ 20 Output, 75 Ω CML Compatible Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC coupling capacitors
OUT0- 19 Output, 75 Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and non-inverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC coupling capacitors
OUT1- 22 Output, Analog
POWER
VDD 7, 21 2.5 V Supply 2.5 V ± 5%
VSS 10, 24 Ground Connect directly to ground (GND)
DAP Ground Exposed DAP, connect to GND using at least 5 vias (see Figure 23 )

Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND

PIN I/O DESCRIPTION
NAME NO.
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
ADDR0 2 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note SMBus section for further details. The four strap options include:
1 kΩ to VDD:
  • Represents logic state 11’b

Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
  • Represents logic state 01'b

1 kΩ to GND:
  • Represents logic state 00'b
ADDR1 15
SCL 3 Input, 2-Level SMBus clock input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3 V LVCMOS tolerant.
SDA 4 I/O, Open Drain, 2-Level SMBus data input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3 V LVCMOS tolerant.
RESERVED 5,14,17,
18		 No Connect
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default): Reserved
20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOS_INT_N 13 Output, LVCMOS
Open Drain, 2-Level 		Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pull-up resistor is required. This pin is 3.3 V LVCMOS tolerant.
LOCK 16 Output, 2.5 V LVCMOS, 2-Level Indicates CDR lock Status
High:
  • CDR locked

Low:
  • CDR not locked
HIGH SPEED DIFFERENTIAL I/O
IN0+ 11 Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors.
IN0- 12 Input, Analog
IN1+ 8 Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors.
IN1- 9 Input, Analog
OUT0+ 20 Output, 75 Ω CML Compatible Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC coupling capacitors
OUT0- 19 Output, 75 Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and non-inverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC coupling capacitors
OUT1- 22 Output, Analog
VDD 7, 21 2.5 V Supply 2.5V ± 5%
VSS 10, 24 Ground Connect directly to ground (GND)
DAP Ground Exposed DAP, connect to GND using at least 5 vias (see Figure 23 )

 
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