SBOS730A April   2015  – May 2015 LMH6401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Setup Diagrams
    2. 8.2 Output Measurement Reference Points
    3. 8.3 ATE Testing and DC Measurements
    4. 8.4 Frequency Response
    5. 8.5 Distortion
    6. 8.6 Noise Figure
    7. 8.7 Pulse Response, Slew Rate, and Overdrive Recovery
    8. 8.8 Power Down
    9. 8.9 VOCM Frequency Response
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Power-Down (PD)
      3. 9.4.3 Thermal Feedback Control
      4. 9.4.4 Gain Control
    5. 9.5 Programming
      1. 9.5.1 Details of the Serial Interface
      2. 9.5.2 Timing Diagrams
    6. 9.6 Register Maps
      1. 9.6.1 Revision ID (address = 0h, Read-Only) [default = 03h]
      2. 9.6.2 Product ID (address = 1h, Read-Only) [default = 00h]
      3. 9.6.3 Gain Control (address = 2h) [default = 20h]
      4. 9.6.4 Reserved (address = 3h) [default = 8Ch]
      5. 9.6.5 Thermal Feedback Gain Control (address = 4h) [default = 27h]
      6. 9.6.6 Thermal Feedback Frequency Control (address = 5h) [default = 45h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Analog Input Characteristics
      2. 10.1.2 Analog Output Characteristics
        1. 10.1.2.1 Driving Capacitive Loads
      3. 10.1.3 Thermal Feedback Control
        1. 10.1.3.1 Step Response Optimization using Thermal Feedback Control
      4. 10.1.4 Thermal Considerations
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Driving ADCs
          1. 10.2.2.1.1 SNR Considerations
          2. 10.2.2.1.2 SFDR Considerations
          3. 10.2.2.1.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
          4. 10.2.2.1.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Do:
      2. 10.3.2 Don't:
  11. 11Power-Supply Recommendations
    1. 11.1 Single-Supply Operation
    2. 11.2 Split-Supply Operation
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
  • Gain Range: –6 dB to 26 dB in 1-dB Steps
  • Differential Input Impedance: 100 Ω
  • Differential Output with Common-Mode Control
  • Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
    • 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
    • 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
    • 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
    • 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
  • Output IP3:
    • 43 dBm at 200 MHz
    • 33 dBm at 1 GHz
    • 27 dBm at 2 GHz
  • Output IP2:
    • 67 dBm at 200 MHz
    • 60 dBm at 1 GHz
    • 52 dBm at 2 GHz
  • 8-dB Noise Figure at 1 GHz, RS = 100 Ω
  • 82-ps Rise, Fall Time Pulse Response
  • Supply Operation: 5.0 V at 69 mA
  • Supports Single- and (±) Split-Supply Operation:
    • DC- and AC-Coupled Applications
  • Fabricated on an Advanced Complementary BiCMOS Process
  • 3-mm × 3-mm UQFN-16 Package

2 Applications

  • Test and Measurement
  • Ultra-Wideband ADC Drivers
  • Communications Receivers
  • RF Sampling Subsystems
  • SAW Filter Buffers and Drivers
  • Defense and Radar

3 Description

The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).

Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.

Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.

This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH6401 UQFN (16) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Harmonic Distortion vs Frequency (VO = 2 VPPD)

LMH6401 D038_SBOS730_LMH6401.gif

IF Sampling Receiver Application

LMH6401 fbd_sbos730.gif