LMK04714-Q1 Automotive Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner

1 Features

AEC-Q100 Grade 1: –40°C to 125°C
Maximum clock output frequency: 3255 MHz
Multi-mode: dual PLL, single PLL, and clock distribution
6-GHz external VCO or distribution input
Ultra-low noise, at 2500 MHz:
- 54-fs RMS jitter (12 kHz to 20 MHz)
- 64-fs RMS jitter (100 Hz to 20 MHz)
- –157.6-dBc/Hz noise floor
Ultra-low noise, at 3200 MHz:
- 61-fs RMS jitter (12 kHz to 20 MHz)
- 67-fs RMS jitter (100 Hz to 100 MHz)
- –156.5-dBc/Hz noise floor
PLL2
- PLL FOM of –230 dBc/Hz
- PLL 1/f of –128 dBc/Hz
- Phase detector rate up to 320 MHz
- Two integrated VCOs: 2440 to 2600 MHz
  and 2945 to 3255 MHz
Up to 14 differential device clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
Up to 1 buffered VCXO/XO output
- LVPECL, LVDS, 2xLVCMOS programmable
1-1023 CLKOUT integer divider
1-8191 SYSREF integer divider
25-ps step analog delay for SYSREF clocks
Digital delay and dynamic digital delay for device clocks and SYSREF
Holdover mode with PLL1
0-delay with PLL1 or PLL2
High Reliability
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability