Loading [MathJax]/jax/output/SVG/fonts/TeX/fontdata.js
Menu
Product
Email
PDF
Order now
LMK1D210x Low Additive Jitter LVDS Buffer
SNAS822B
September 2021 – June 2023
LMK1D2102
,
LMK1D2104
PRODUCTION DATA
CONTENTS
SEARCH
LMK1D210x Low Additive Jitter LVDS Buffer
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Fail-Safe Inputs
9.4
Device Functional Modes
9.4.1
LVDS Output Termination
9.4.2
Input Termination
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
10.3
Power Supply Recommendations
10.4
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RHD|28
MPQF133F
Thermal pad, mechanical data (Package|Pins)
RHD|28
QFND050K
Orderable Information
snas822b_oa
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content
Data Sheet
LMK1D210x Low Additive Jitter LVDS Buffer