LMV34x-N Single Rain-to-Rail Output CMOS Operation Amplifier With Shutdown
- SNOS990H April 2002 – June 2016 LMV341-N , LMV342-N , LMV344-N
  
  PRODUCTION DATA.

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DATA SHEET

LMV34x-N Single Rain-to-Rail Output CMOS Operation Amplifier With Shutdown

1 Features

Typical 2.7 V Supply Values (Unless Otherwise Noted)
Ensured 2.7 V and 5 V Specifications
Input Referred Voltage Noise at 10 kHz:
29 nV/√Hz
Supply Current (Per Amplifier): 100 µA
Gain Bandwidth Product: 1 MHz
Slew Rate: 1 V/µs
Shutdown Current (LMV341-N): 45 pA
Turnon Time From Shutdown (LMV341-N): 5 µs
Input Bias Current: 20 fA

2 Applications

Cordless or Cellular Phones
Laptops
PDAs
PCMCIA or Audio
Portable or Battery-Powered Electronic Equipment
Supply Current Monitoring
Battery Monitoring
Buffers
Filters
Drivers

Sample and Hold Circuit

3 Description

The LMV34x-N devices are single, dual, and quad low-voltage, low-power operational amplifiers. They are designed specifically for low-voltage portable applications. Other important product characteristics are low input bias current, rail-to-rail output, and wide temperature range.

The patented class AB turnaround stage significantly reduces the noise at higher frequencies, power consumption, and offset voltage. The PMOS input stage provides the user with ultra-low input bias current of 20 fA (typical) and high input impedance.

The industrial-plus temperature range of −40°C to 125°C allows the LMV34x-N to accommodate a broad range of extended environment applications. LMV341-N expands Texas Instrument's Silicon Dust amplifier portfolio offering enhancements in size, speed, and power savings. The LMV34x-N devices are specified to operate over the voltage range of
2.7 V to 5.5 V and all have rail-to-rail output.

The LMV341-N offers a shutdown pin that can be used to disable the device. Once in shutdown mode, the supply current is reduced to 45 pA (typical). The LMV34x-N devices have 29-nV voltage noise at 10 KHz, 1 MHz GBW, 1-V/µs slew rate, 0.25 mVos, and 0.1-µA shutdown current (LMV341-N).

The LMV341-N is offered in the tiny 6-pin SC70 package, the LMV342-N in space-saving 8-pin VSSOP and SOIC packages, and the LMV344-N in 14-pin TSSOP and SOIC packages. These small package amplifiers offer an ideal solution for applications requiring minimum PCB footprint. Applications with area constrained PCB requirements include portable electronics such as cellular handsets and PDAs.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMV341-N	SC70 (6)	2.00 mm × 1.25 mm
LMV342-N	VSSOP (8)	3.00 mm × 3.00 mm
LMV342-N	SOIC (8)	4.90 mm × 3.91 mm
LMV344-N	TSSOP (14)	5.00 mm × 4.40 mm
LMV344-N	SOIC (14)	8.64 mm × 3.91 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from G Revision (March 2013) to H Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Changed Thermal Information tableGo

Changes from F Revision (March 2012) to G Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

DCK Package

6-Pin SC70

Top View

LMV341-N LMV342-N LMV344-N sc70_diag.gif

Pin Functions – LMV341-N

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
+IN	1	I	Noninverting input
–IN	3	I	Inverting input
GND	2	P	Negative supply input
OUT	4	O	Output
V⁺	6	P	Positive supply input
SHDN	5	I	Active low enable input

(1) I = Input, O = Output, and P = Power

DGK or D Package

8-Pin VSSOP or SOIC

Top View

Pin Functions – LMV342-N

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
IN A⁺	3	I	Noninverting input, channel A
IN A^–	2	I	Inverting input, channel A
IN B⁺	5	I	Noninverting input, channel B
IN B^–	6	I	Inverting input, channel B
OUT A	1	O	Output, channel A
OUT B	7	O	Output, channel B
V⁺	8	P	Positive (highest) power supply
V^–	4	P	Negative (lowest) power supply

(1) I = Input, O = Output, and P = Power

PW or D Package

14-Pin TSSOP or SOIC

Top View

Pin Functions – LMV344-N

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
IN A⁺	3	I	Noninverting input, channel A
IN A^–	2	I	Inverting input, channel A
IN B⁺	5	I	Noninverting input, channel B
IN B^–	6	I	Inverting input, channel B
IN C⁺	10	I	Noninverting input, channel C
IN C^–	9	I	Inverting input, channel C
IN D⁺	12	I	Noninverting input, channel D
IN D^–	13	I	Inverting input, channel D
OUT A	1	O	Output, channel A
OUT B	7	O	Output, channel B
OUT C	8	O	Output, channel C
OUT D	14	O	Output, channel D
V⁺	4	P	Positive (highest) power supply
V^–	11	P	Negative (lowest) power supply

(1) I = Input, O = Output, and P = Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Differential input voltage		±Supply voltage
Supply voltage (V⁺ – V^–)			6	V
Output short circuit to V⁺		See⁽³⁾
Output short circuit to V^–		See⁽⁴⁾
Lead temperature	Infrared or convection reflow (20 s)		235	°C
Lead temperature	Wave soldering (10 s)		260	°C
Junction temperature, T_J⁽⁵⁾			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) Shorting output to V⁺ will adversely affect reliability.

(4) Shorting output to V^- will adversely affect reliability.

(5) The maximum power dissipation is a function of T_J(MAX), R_θJA. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) – T_A) / R_θJA. All numbers apply for packages soldered directly onto a PCB.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM)⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Machine model (MM)⁽²⁾	±200	V

(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.

(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage		2.7	5.5	V
Temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMV341-N	LMV342-N		LMV344-N		UNIT
		DCK (SC70)	D (SOIC)	DGK (VSSOP)	D (SOIC)	PW (TSSOP)
		6 PINS	8 PINS	8 PINS	14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	414	190	235	145	155	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	116.1	65.2	68.4	45.9	50.5	°C/W
R_θJB	Junction-to-board thermal resistance	53.3	61.4	98.8	44.1	66.2	°C/W
ψ_JT	Junction-to-top characterization parameter	8.8	16.1	9.8	10.2	6.3	°C/W
ψ_JB	Junction-to-board characterization parameter	52.7	60.8	97.3	43.7	65.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	—	—	—	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics – 2.7 V (DC)

T_J = 25°C, V⁺ = 2.7 V, V^– = 0 V, V_CM = V⁺/ 2, V_O = V⁺/ 2, and R_L > 1 MΩ (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN⁽²⁾	TYP⁽³⁾	MAX⁽²⁾	UNIT
V_OS	Input offset voltage	LMV341-N	T_J = 25°C		0.25	4	mV
		LMV341-N	−40°C ≤ T_J ≤ 125°C			4.5
		LMV342-N and LMV344-N	T_J = 25°C		0.55	5
		LMV342-N and LMV344-N	−40°C ≤ T_J ≤ 125°C			5.5
TCV_OS	Input offset voltage average drift				1.7		µV/°C
I_B	Input bias current	T_J = 25°C			0.02	120	pA
I_B	Input bias current	-40°C ≤ T_J ≤ 150°C				250	pA
I_OS	Input offset current				6.6		fA
I_S	Supply current	Per amplifier	T_J = 25°C		100	170	µA
		Per amplifier	−40°C ≤ T_J ≤ 125°C			230
		Shutdown mode, V_SD = 0 V, LMV341-N	T_J = 25°C		4.5 × 10^–5	1
		Shutdown mode, V_SD = 0 V, LMV341-N	−40°C ≤ T_J ≤ 125°C			1.5
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 1.7 V, 0 V ≤ V_CM ≤ 1.6 V	T_J = 25°C	56	80		dB
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 1.7 V, 0 V ≤ V_CM ≤ 1.6 V	−40°C ≤ T_J ≤ 125°C	50			dB
PSRR	Power supply rejection ratio	2.7 V ≤ V⁺ ≤ 5 V	T_J = 25°C	65	82		dB
PSRR	Power supply rejection ratio	2.7 V ≤ V⁺ ≤ 5 V	−40°C ≤ T_J ≤ 125°C	60			dB
V_CM	Input common-mode voltage	For CMRR ≥ 50 dB	V+		1.9	1.7	V
V_CM	Input common-mode voltage	For CMRR ≥ 50 dB	V–	0	−0.2		V
A_V	Large signal voltage gain	R_L = 10 kΩ to 1.35 V	T_J = 25°C	78	113		dB
		R_L = 10 kΩ to 1.35 V	–40°C ≤ T_J ≤ 125°C	70
		R_L = 2 kΩ to 1.35 V	T_J = 25°C	72	103
		R_L = 2 kΩ to 1.35 V	–40°C ≤ T_J ≤ 125°C	64
V_O	Output swing	R_L = 2 kΩ to 1.35 V	T_J = 25°C		24	60	mV
			–40°C ≤ T_J ≤ 125°C			95
			T_J = 25°C	60	26
			–40°C ≤ T_J ≤ 125°C	95
		R_L = 10 kΩ to 1.35 V	T_J = 25°C		5	30
			–40°C ≤ T_J ≤ 125°C			40
			T_J = 25°C	30	5.3
			–40°C ≤ T_J ≤ 125°C	40
I_O	Output short-circuit current	Sourcing, LMV341-N and LMV342-N		20	32		mA
		Sourcing, LMV344-N		18	24
		Sinking		15	24
t_on	Turnon time from shutdown	LMV341-N			5		µs
V_SD	Shutdown pin voltage	ON mode, LMV341-N		2.4	1.7	2.7	V
V_SD	Shutdown pin voltage	Shutdown mode, LMV341-N		0	1	0.8	V

(1) Electrical characteristic values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that T_J = T_A. No specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T_J > T_A.

(2) All limits are specified by testing or statistical analysis.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material.

6.6 Electrical Characteristics – 2.7 V (AC)

T_J = 25°C, V⁺ = 2.7V, V⁻ = 0V, V_CM = V⁺/ 2, V_O = V⁺/ 2, and R_L > 1 MΩ (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	TYP⁽³⁾	UNIT
SR	Slew rate	R_L = 10 kΩ⁽⁴⁾	1	V/µs
GBW	Gain bandwidth product	R_L = 100 kΩ, C_L = 200 pF	1	MHz
Φ_m	Phase margin	R_L = 100 kΩ	72	°
G_m	Gain margin	R_L = 100 kΩ	20	dB
e_n	Input-referred voltage noise	f = 1 kHz	40	nV/√Hz
i_n	Input-referred current noise	f = 1 kHz	0.001	pA/√Hz
THD	Total harmonic distortion	f = 1 kHz, A_V = +1, R_L = 600 Ω, V_IN = 1V_PP	0.017%

(2) All limits are specified by testing or statistical analysis.

(4) Connected as voltage follower with 2-V_PP step input. Number specified is the slower of the positive and negative slew rates.

6.7 Electrical Characteristics – 5 V (DC)

T_J = 25°C, V⁺ = 5 V, V⁻ = 0 V, V_CM = V⁺/ 2, V_O = V⁺/ 2, and R_L > 1 MΩ (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN⁽²⁾	TYP⁽³⁾	MAX⁽²⁾	UNIT
V_OS	Input offset voltage	LMV341-N	T_J = 25°C		0.025	4	mV
		LMV341-N	–40°C ≤ T_J ≤ 125°C			4.5
		LMV342-N and LMV344-N	T_J = 25°C		0.7	5
		LMV342-N and LMV344-N	–40°C ≤ T_J ≤ 125°C			5.5
TCV_OS	Input offset voltage average drift				1.9		µV/°C
I_B	Input bias current	T_J = 25°C			0.02	200	pA
I_B	Input bias current	–40°C ≤ T_J ≤ 125°C				375	pA
I_OS	Input offset current				6.6		fA
I_S	Supply current	Per amplifier	T_J = 25°C		107	200	µA
		Per amplifier	–40°C ≤ T_J ≤ 125°C			260
		Shutdown mode, V_SD = 0 V, LMV341-N	T_J = 25°C		0.033	1
		Shutdown mode, V_SD = 0 V, LMV341-N	–40°C ≤ T_J ≤ 125°C			1.5
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 4 V, 0 V ≤ V_CM ≤ 3.9 V	T_J = 25°C	56	86		dB
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 4 V, 0 V ≤ V_CM ≤ 3.9 V	–40°C ≤ T_J ≤ 125°C	50			dB
PSRR	Power supply rejection ratio	2.7 V ≤ V⁺ ≤ 5 V	T_J = 25°C	65	82		dB
PSRR	Power supply rejection ratio	2.7 V ≤ V⁺ ≤ 5 V	–40°C ≤ T_J ≤ 125°C	60			dB
V_CM	Input common-mode voltage	For CMRR ≥ 50 dB	V+		4.2	4	V
V_CM	Input common-mode voltage	For CMRR ≥ 50 dB	V–	0	−0.2		V
A_V	Large signal voltage gain⁽⁴⁾	R_L = 10 kΩ to 2.5 V	T_J = 25°C	78	116		dB
		R_L = 10 kΩ to 2.5 V	–40°C ≤ T_J ≤ 125°C	70
		R_L = 2 kΩ to 2.5 V	T_J = 25°C	72	107
		R_L = 2 kΩ to 2.5 V	–40°C ≤ T_J ≤ 125°C	64
V_O	Output swing	R_L = 2 kΩ to 2.5 V	T_J = 25°C		32	60	mV
			–40°C ≤ T_J ≤ 125°C			95
			T_J = 25°C	60	34
			–40°C ≤ T_J ≤ 125°C	95
		R_L = 10 kΩ to 2.5 V	T_J = 25°C		7	30
			–40°C ≤ T_J ≤ 125°C			40
			T_J = 25°C	30	7
			–40°C ≤ T_J ≤ 125°C	40
I_O	Output short-circuit current	Sourcing		85	113		mA
I_O	Output short-circuit current	Sinking		50	75		mA
t_on	Turnon time from shutdown	LMV341-N			5		µs
V_SD	Shutdown pin voltage	ON mode, LMV341-N		4.5	3.1	5	V
V_SD	Shutdown pin voltage	Shutdown mode, LMV341-N		0	1	0.8	V

(2) All limits are specified by testing or statistical analysis.

(4) R_L is connected to mid-supply. The output voltage is GND + 0.2 V ≤ V_O ≤ V⁺– 0.2 V

6.8 Electrical Characteristics – 5 V (AC)

T_J = 25°C, V⁺ = 5 V, V⁻ = 0 V, V_CM = V⁺/ 2, V_O = V⁺/ 2 and R_L > 1 MΩ (unless otherwise noted)⁽¹⁾

PARAMETER		CONDITIONS	TYP⁽³⁾	UNIT
SR	Slew rate	R_L = 10 kΩ⁽⁴⁾	1	V/µs
GBW	Gain-bandwidth product	R_L = 10 kΩ, C_L = 200 pF	1	MHz
Φ_m	Phase margin	R_L = 100 kΩ	70	deg
G_m	Gain margin	R_L = 100 kΩ	20	dB
e_n	Input-referred voltage noise	f = 1 kHz	39	nV/√Hz
i_n	Input-referred current noise	f = 1 kHz	0.001	pA/√Hz
THD	Total harmonic distortion	f = 1 kHz, A_V = +1, R_L = 600 Ω, V_IN = 1V_PP	0.012%

(2) All limits are specified by testing or statistical analysis.

(4) Connected as voltage follower with 2-V_PP step input. Number specified is the slower of the positive and negative slew rates.

6.9 Typical Characteristics

Figure 1. Supply Current vs Supply Voltage (LMV341-N)

Figure 3. Output Voltage Swing vs Supply Voltage

Figure 5. I_SOURCE vs V_OUT

Figure 7. I_SINK vs V_OUT

Figure 9. V_OS vs V_CM

Figure 11. V_IN vs V_OUT

Figure 13. CMRR vs Frequency

Figure 15. Input Voltage Noise vs Frequency

Figure 17. Slew Rate vs Temperature

Figure 19. THD+N vs Frequency

Figure 21. Open-Loop Frequency Over Temperature

Figure 23. Open-Loop Frequency Response

Figure 25. Gain and Phase vs C_L

Figure 27. Stability vs Capacitive Load

Figure 29. Noninverting Large Signal Pulse Response

Figure 31. Noninverting Large Signal Pulse Response

Figure 33. Noninverting Large Signal Pulse Response

Figure 35. Inverting Large Signal Pulse Response

Figure 37. Inverting Large Signal Pulse Response

Figure 39. Inverting Large Signal Pulse Response

Figure 2. Input Current vs Temperature

Figure 4. Output Voltage Swing vs Supply Voltage

Figure 6. I_SOURCE vs V_OUT

Figure 8. I_SINK vs V_OUT

Figure 10. V_OS vs V_CM

Figure 12. V_IN vs V_OUT

Figure 14. PSRR vs Frequency

Figure 16. Slew Rate vs V_SUPPLY

Figure 18. Slew Rate vs Temperature

Figure 20. THD+N vs V_OUT

Figure 22. Open-Loop Frequency Response

Figure 24. Gain and Phase vs C_L

Figure 26. Stability vs Capacitive Load

Figure 28. Noninverting Small Signal Pulse Response

Figure 30. Noninverting Small Signal Pulse Response

Figure 32. Noninverting Small Signal Pulse Response

Figure 34. Inverting Small Signal Pulse Response

Figure 36. Inverting Small Signal Pulse Response

Figure 38. Inverting Small Signal Pulse Response

Figure 40. Crosstalk Rejection vs Frequency

7 Detailed Description

7.1 Overview

TI’s LMV34x-N family of amplifiers have 1-MHz bandwidth, 1-V/µs slew rate, a rail-to-rail output stage, and consume only 100 µA of current per amplifier while active. When in shutdown mode it only consumes 45-pA supply consumption with only 20 fA of input bias current. Lastly, these operational amplifiers provide an input-referred voltage noise 29 nV√Hz (at 10 kHz).

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Class AB Turnaround Stage Amplifier

This patented folded cascode stage has a combined class AB amplifier stage, which replaces the conventional folded cascode stage. Therefore, the class AB folded cascode stage runs at a much lower quiescent current compared to conventional-folded cascode stages. This results in significantly smaller offset and noise contributions. The reduced offset and noise contributions in turn reduce the offset voltage level and the voltage noise level at the input of LMV34x-N. Also the lower quiescent current results in a high open-loop gain for the amplifier. The lower quiescent current does not affect the slew rate of the amplifier nor its ability to handle the total current swing coming from the input stage.

The input voltage noise of the device at low frequencies, below 1 kHz, is slightly higher than devices with a BJT input stage; however, the PMOS input stage results in a much lower input bias current and the input voltage noise drops at frequencies above 1 kHz.

7.4 Device Functional Modes

7.4.1 Shutdown Feature

The LMV341-N is capable of being turned off to conserve power and increase battery life in portable devices. Once in shutdown mode the supply current is drastically reduced, 1-µA maximum, and the output is tri-stated.

The device is disabled when the shutdown pin voltage is pulled low. The shutdown pin must never be left unconnected. Leaving the pin floating results in an undefined operation mode and the device may oscillate between shutdown and active modes.

The LMV341-N typically turns on 2.8 µs after the shutdown voltage is pulled high. The device turns off in less than 400 ns after shutdown voltage is pulled low. Figure 41 and Figure 42 show the turnon and turnoff time of the LMV341-N, respectively. To reduce the effect of the capacitance added to the circuit by the scope probe, in the turnoff time circuit a resistive load of 600 Ω is added. Figure 43 and Figure 44 show the test circuits used to obtain the two plots.

Figure 41. Turnon Time Plot

Figure 43. Turnon Time Circuit

Figure 42. Turnoff Time Plot

Figure 44. Turnoff Time Circuit

7.4.2 Low Input Bias Current

LMV34x-N amplifiers have a PMOS input stage. As a result, they have a much lower input bias current than devices with BJT input stages. This feature makes these devices ideal for sensor circuits. A typical curve of the input bias current of the LMV341-N is shown in Figure 45.

Figure 45. Input Bias Current vs V_CM

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV34x-N amplifier family features low voltage, low power, rail-to-rail output as well as a shutdown capability, making it well suited for low voltage portable applications.

8.2 Typical Application

8.2.1 Sample and Hold Circuit

Figure 46. Sample and Hold Circuit

8.2.1.1 Design Requirements

The lower input bias current of the LMV341-N results in a very high input impedance. The output impedance when the device is in shutdown mode is quite high. These high impedances, along with the ability of the shutdown pin to be derived from a separate power source, make LMV341-N a good choice for sample and hold circuits. The sample clock must be connected to the shutdown pin of the amplifier to rapidly turn the device on or off.

8.2.1.2 Detailed Design Procedure

Figure 46 shows the schematic of a simple sample and hold circuit. When the sample clock is high the first amplifier is in normal operation mode and the second amplifier acts as a buffer. The capacitor, which appears as a load on the first amplifier, is charging at this time. The voltage across the capacitor is that of the noninverting input of the first amplifier because it is connected as a voltage-follower. When the sample clock is low the first amplifier is shut off, bringing the output impedance to a high value. The high impedance of this output, along with the very high impedance on the input of the second amplifier, prevents the capacitor from discharging. There is very little voltage droop while the first amplifier is in shutdown mode. The second amplifier, which is still in normal operation mode and is connected as a voltage follower, also provides the voltage sampled on the capacitor at its output.

8.2.1.3 Application Curve

LMV341-N LMV342-N LMV344-N TYP_APP_SNOSC70_a.png

Figure 47. Sample and Hold Circuit Results