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  • LMV55x 3-MHz, Micropower RRO Amplifiers

    • SNOSAQ5H February   2007  – August 2016 LMV551 , LMV552 , LMV554

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • LMV55x 3-MHz, Micropower RRO Amplifiers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 3 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Voltage and Low Power Operation
      2. 7.3.2 Wide Bandwidth
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Ground Sensing and Rail-to-Rail Output
      5. 7.3.5 Small Size
    4. 7.4 Device Functional Modes
      1. 7.4.1 Stability Of Op Amp Circuits
        1. 7.4.1.1 Stability and Capacitive Loading
          1. 7.4.1.1.1 In the Loop Compensation
          2. 7.4.1.1.2 Compensation by External Resistor
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
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DATA SHEET

LMV55x 3-MHz, Micropower RRO Amplifiers

1 Features

  • Specified 3-V and 5-V Performance
  • High Unity Gain Bandwidth 3 MHz
  • Supply Current (Per Amplifier) 37 µA
  • CMRR 93 dB
  • PSRR 90 dB
  • Slew Rate 1 V/µs
  • Output Swing With 100-kΩ Load 70 mV From Rail
  • Total Harmonic Distortion: 0.003% at 1 kHz, 2 kΩ
  • Temperature Range: −40°C to 125°C

2 Applications

  • Active Filters
  • Portable Equipment
  • Automotive
  • Battery Powered Systems
  • Sensors and Instrumentation

3 Description

The LMV55x are high-performance, low-power operational amplifiers implemented with TI’s advanced VIP50 process. They feature 3 MHz of bandwidth while consuming only 37 µA of current per amplifier, which is an exceptional bandwidth to power ratio in this op amp class. These ultra-low power amplifiers are unity gain stable and provide an excellent solution for ultra-low power applications requiring a wide bandwidth.

The LMV55x have a rail-to-rail output stage and an input common mode range that extends below ground.

The LMV55x have an operating supply voltage range from 2.7 V to 5.5 V. These amplifiers can operate over a wide temperature range (−40°C to 125°C), making them a great choice for automotive applications, sensor applications as well as portable instrumentation applications. The LMV551 is offered in the ultra tiny 5-Pin SC70 and 5-Pin SOT-23 package. The LMV552 is offered in an 8-Pin VSSOP package. The LMV554 is offered in the 14-Pin TSSOP.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM551 SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
LMV552 VSSOP (8) 3.00 mm × 3.00 mm
LMV554 TSSOP (14) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

LMV551 LMV552 LMV554 20152601.gif

Open Loop Gain and Phase vs Frequency

LMV551 LMV552 LMV554 20152613.gif

4 Revision History

Changes from G Revision (February 2013) to H Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed values in the Thermal Information table to align with JEDEC standards.Go

Changes from F Revision (February 2013) to G Revision

  • Changed layout of National Semiconductor Data Sheet to TI format.Go

5 Pin Configuration and Functions

DBV and DCK Packages
5-Pin SOT-23 and SC70
Top View
LMV551 LMV552 LMV554 20152602.gif
DGK Package
8-Pin VSSOP
Top View
LMV551 LMV552 LMV554 20152611.gif
PW Package
14-Pin TSSOP
Top View
LMV551 LMV552 LMV554 20152610.gif

Pin Functions: LMV551

PIN TYPE(1) DESCRIPTION
NAME LMV551
SOT-23, SC70
+IN 1 I Noninverting Input
-IN 3 I Inverting Input
OUT 4 O Output
V- 2 P Negative Supply
V+ 5 P Positive Supply
(1) I = Input; O = Output; P = Power

Pin Functions: LMV552 and LMV554

PIN TYPE(1) DESCRIPTION
NAME LMV552 LMV554
SOIC, VSSOP SOIC, TSSOP
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
+IN C — 10 I Noninverting input, channel C
+IN D — 12 I Noninverting input, channel D
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
–IN C — 9 I Inverting input, channel C
–IN D — 13 I Inverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C — 8 O Output, channel C
OUT D — 14 O Output, channel D
V+ 8 4 P Positive (highest) power supply
V– 4 11 P Negative (lowest) power supply
(1) I = Input; O = Output; P = Power

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN Differential (at V+ = 5 V) ±2.5 V
Supply voltage (V+ – V−) 6 V
Voltage at input/output pins V− –0.3 V+ +0.3 V
Junction temperature, TJ (3) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2000 V
Machine model (MM)(2) LMV551 ±100
LMV552 / LMV554 ±250
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.
(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Temperature (1) –40 125 °C
Supply voltage (V+ – V−) 2.7 5.5 V
(1) The maximum power dissipation is a function of TJ(MAX), θJA, The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.4 Thermal Information

THERMAL METRIC(1) LMV551 LMV552 LMV554 UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DGK
(VSSOP)		 PW
(TSSOP)
5 PINS 5 PINS 8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 213.6 303.5 200.3 134.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 174.8 135.5 89.1 60.9 °C/W
RθJB Junction-to-board thermal resistance 72.6 81.1 120.9 77.3 °C/W
ψJT Junction-to-top characterization parameter 56.6 8.4 21.7 11.5 °C/W
ψJB Junction-to-board characterization parameter 72.2 80.4 119.4 76.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: 3 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3 V, V− = 0 V, VCM = V+/2 = VO. (1)
PARAMETER TEST CONDITIONS MIN
(2)		 TYP(2) MAX(2) UNIT
VOS Input offset voltage TA = 25°C 1 3 mV
TA = –40°C to 125°C 4.5
TC VOS Input offset average drift TA = –40°C to 125°C 3.3 µV/°C
IB Input bias current(3) TA = 25°C 20 38 nA
IOS Input offset current TA = 25°C 1 20 nA
CMRR Common mode rejection ratio 0 V ≤ VCM 2 V TA = 25°C 74 92 dB
TA = –40°C to +125°C 72
PSRR Power supply rejection ratio 3 ≤ V+ ≤ 5 V,
VCM = 0.5 V		 LMV551 and LMV552 TA = 25°C 80 92 dB
TA = –40°C to +125°C 78
LMV554 TA = 25°C 78 92
TA = –40°C to +125°C 76
2.7 ≤ V+ ≤ 5.5 V,
VCM = 0.5 V		 LMV551 and LMV552 TA = 25°C 80 92
TA = –40°C to +125°C 78
LMV554 TA = 25°C 78 92
TA = -40°C to +125°C 76
CMVR Input common-mode voltage CMRR ≥ 68 dB TA = 25°C 0 2.1 V
CMRR ≥ 60 dB TA = -40°C to +125°C 0 2.1
AVOL Large signal voltage gain 0.4 ≤ VO ≤ 2.6,
RL = 100 kΩ to V+/2		 LMV551 and LMV552 TA = 25°C 81 90 dB
TA = –40°C to +125°C 78
LMV554 TA = 25°C 79 90
TA = –40°C to +125°Ce 77
0.4 ≤ VO ≤ 2.6, RL = 10 kΩ to V+/2 TA = 25°C 71 80
TA = -40°C to +125°C 68
VO Output swing high RL = 100 kΩ to V+/2 TA = 25°C 40 48 mV from rail
TA = –40°C to +125°C 58
RL = 10 kΩ to V+/2 TA = 25°C 85 100
TA = –40°C to +125°C 120
Output swing low RL = 100 kΩ to V+/2 TA = 25°C 50 65
TA = –40°C to +125°C 77
RL = 10 kΩ to V+/2 TA = 25°C 95 110
TA = –40°C to +125°C 130
ISC Output short circuit current Sourcing (5) 10 mA
Sinking (5) 25
IS Supply current per amplifier TA = 25°C 34 42 µA
TA = –40°C to +125°C 52
SR Slew rate AV = +1,
10% to 90% (4)		 1 V/µs
Φm Phase margin RL = 10 kΩ, CL = 20 pF 75 °
GBW Gain bandwidth product 3 MHz
en Input-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
In Input-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.003%
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Positive current corresponds to current flowing into the device.
(4) Slew rate is the average of the rising and falling slew rates.
(5) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.

6.6 Electrical Characteristics: 5 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2 = VO. (1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage TA = 25°C 1 3 mV
TA = –40°C to +125°C 4.5
TC VOS Input offset average drift TA = 25°C 3.3 µV/°C
IB Input bias current (4) TA = 25°C 20 38 nA
IOS Input offset current 1 20 nA
CMRR Common mode rejection ratio TA = 25°C 76 93 nA
TA = –40°C to +125°C 74
PSRR Power supply rejection ratio 3 V ≤ V+ ≤ 5 V to VCM = 0.5 V TA = 25°C 78 90 dB
TA = –40°C to +125°C 75
2.7 V ≤ V+ ≤ 5.5 V to VCM = 0.5 V TA = 25°C 78 90
TA = –40°C to +125°C 75
CMVR Input common-mode voltage CMRR ≥ 68 dB
CMRR ≥ 60 dB		 TA = 25°C 0 4.1 V
TA = –40°C to +125°C 0 4.1
AVOL Large signal voltage gain 0.4 ≤ VO ≤ 4.6, RL = 100 kΩ to V+/2 78 90 dB
75
0.4 ≤ VO ≤ 4.6, RL = 10 kΩ to V+/2 75 80
72
VO Output swing high RL = 100 kΩ to V+/2 TA = 25°C 70 92 mV from rail
TA = –40°C to +125°C 122
RL = 10 kΩ to V+/2 TA = 25°C 125 155
TA = –40°C to +125°C 210
Output swing low RL = 100 kΩ to V+/2 TA = 25°C 60 70
TA = –40°C to +125°C 82
RL = 10 kΩ to V+/2 TA = 25°C 110 130
TA = –40°C to +125°C 155
ISC Output short-circuit current Sourcing (5) 10 mA
Sinking (5) 25
IS Supply current per amplifier TA = 25°C 37 46 µA
TA = –40°C to +125°C 54
SR Slew rate AV = +1, VO = 1 VPP
10% to 90% (6)		 1 V/µs
Φm Phase margin RL = 10 kΩ, CL = 20 pF 75 °
GBW Gain bandwidth product 3 MHz
en Input-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
In Input-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.003%
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Positive current corresponds to current flowing into the device.
(5) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.
(6) Slew rate is the average of the rising and falling slew rates.

6.7 Typical Characteristics

LMV551 LMV552 LMV554 20152614.gif
Figure 1. Open-Loop Gain and Phase With Capacitive Load
LMV551 LMV552 LMV554 20152616.gif
Figure 3. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152618.gif
Figure 5. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152620.gif
Figure 7. Small-Signal Transient Response
LMV551 LMV552 LMV554 20152622.gif
Figure 9. Small-Signal Transient Response
LMV551 LMV552 LMV554 20152624.gif
Figure 11. THD+N vs Amplitude at 3 V
LMV551 LMV552 LMV554 20152626.gif
Figure 13. THD+N vs Amplitude
LMV551 LMV552 LMV554 20152628.gif
Figure 15. Supply Current vs Supply Voltage
LMV551 LMV552 LMV554 20152630.gif
Figure 17. VOS vs VCM
LMV551 LMV552 LMV554 20152632.gif
Figure 19. IBIAS vs VCM
LMV551 LMV552 LMV554 20152634.gif
Figure 21. IBIAS vs Supply Voltage
LMV551 LMV552 LMV554 20152636.gif
Figure 23. Negative Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152638.gif
Figure 25. Negative Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152615.gif
Figure 2. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152617.gif
Figure 4. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152619.gif
Figure 6. Slew Rate vs Supply voltage
LMV551 LMV552 LMV554 20152621.gif
Figure 8. Large-Signal Transient Response
LMV551 LMV552 LMV554 20152623.gif
Figure 10. Input Referred Noise vs Frequency
LMV551 LMV552 LMV554 20152625.gif
Figure 12. THD+N vs Amplitude at 5 V
LMV551 LMV552 LMV554 20152627.gif
Figure 14. THD+N vs Amplitude
LMV551 LMV552 LMV554 20152629.gif
Figure 16. VOS vs VCM
LMV551 LMV552 LMV554 20152631.gif
Figure 18. VOS vs Supply Voltage
LMV551 LMV552 LMV554 20152633.gif
Figure 20. IBIAS vs VCM
LMV551 LMV552 LMV554 20152635.gif
Figure 22. Positive Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152637.gif
Figure 24. Positive Output Swing vs Supply Voltage

7 Detailed Description

7.1 Overview

The LMV55x are high performance, low power operational amplifiers implemented with TI’s advanced VIP50 process. They feature 3 MHz of bandwidth while consuming only 37 µA of current per amplifier, which is an exceptional bandwidth to power ratio in this op amp class. These amplifiers are unity gain stable and provide an excellent solution for low power applications requiring a wide bandwidth.

7.2 Functional Block Diagram

LMV551 LMV552 LMV554 Op_Amp_Triangle_Block_Diagram.png
(Each Amplifier)

7.3 Feature Description

The differential inputs of the amplifier consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp VOUT is given by Equation 1:

Equation 1. VOUT = AOL (IN+ - IN-)

where

  • AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10 uV per volt).

7.3.1 Low Voltage and Low Power Operation

The LMV55x have performance ensured at supply voltages of 3 V and 5 V and are ensured to be operational at all supply voltages from 2.7 V to 5.5 V. For this supply voltage range, the LMV55x draw the extremely low supply current of less than 37 μA per amp.

7.3.2 Wide Bandwidth

The bandwidth to power ratio of 3 MHz to 37 μA per amplifier is one of the best bandwidth to power ratios ever achieved. This makes these devices ideal for low power signal processing applications such as portable media players and instrumentation.

7.3.3 Low Input Referred Noise

The LMV55x provide a flatband input referred voltage noise density of 70 nV/√Hz , which is significantly better than the noise performance expected from an ultra low power op amp. They also feature the exceptionally low 1/f noise corner frequency of 4 Hz. This noise specification makes the LMV55x ideal for low power applications such as PDAs and portable sensors.

7.3.4 Ground Sensing and Rail-to-Rail Output

The LMV55x each have a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing. The input common mode range includes the negative supply rail which allows direct sensing at ground in a single supply operation.

7.3.5 Small Size

The small footprints of the LMV55x packages save space on printed circuit boards, and enable the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, the amplifiers can be placed closer to the signal source, reducing noise pickup and enhancing signal integrity.

7.4 Device Functional Modes

7.4.1 Stability Of Op Amp Circuits

7.4.1.1 Stability and Capacitive Loading

As seen in the Phase Margin vs Capacitive Load graph, the phase margin reduces significantly for CL greater than 100 pF. This is because the op amp is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing them for higher capacitive loads would have required either a drastic increase in supply current, or a large internal compensation capacitance, which would have reduced the bandwidth of the op amp. Hence, if the LMV55x are to be used for driving higher capacitive loads, they must be externally compensated.

LMV551 LMV552 LMV554 20152603.gif Figure 26. Gain vs Frequency for an Op Amp

An op amp, ideally, has a dominant pole close to DC, which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until the op amp’s unity gain bandwidth, the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (Figure 26). This increases the ROC to 40 dB/ decade and causes instability.

In such a case a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which ensures stability.

7.4.1.1.1 In the Loop Compensation

Figure 27 illustrates a compensation technique, known as ‘in the loop’ compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF, is inserted across the feedback resistor to bypass CL at higher frequencies.

LMV551 LMV552 LMV554 20152604.gif Figure 27. In the Loop Compensation

The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for by the presence of the zero, and that the ROC is maintained at 20 dB/decade. For the circuit shown in Figure 27 the values of RS and CF are given by Equation 2. Values of RS and CF required for maintaining stability for different values of CL, as well as the phase margins obtained, are shown in Table 1. RF, RIN, and RL are to be 10 kΩ, while ROUT is 340Ω.

Equation 2. LMV551 LMV552 LMV554 20152605.gif

Table 1. Phase Margins

CL (pF) RS (Ω) CF (pF) PHASE MARGIN (°)
50 340 8 47
100 340 15 42
150 340 22 40

Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth. The closed loop bandwidth of the circuit is now limited by RF and CF.

7.4.1.1.2 Compensation by External Resistor

In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in Figure 28. A resistor, RISO, is placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance and ensures stability. The value of RISO to be used should be decided depending on the size of CL and the level of performance desired. Values ranging from 5 Ω to 50 Ω are usually sufficient to ensure stability. A larger value of RISO results in a system with less ringing and overshoot, but also limits the output swing and the short-circuit current of the circuit.

LMV551 LMV552 LMV554 20152612.gif Figure 28. Compensation by Isolation Resistor

 
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