SNVSA28 December   2014 LP8731-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset Threshold/Function (POR)
    10. 7.10 I2C-Compatible Interface Timing
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1 Linear Low Dropout Regulators (LDOs)
      2. 8.3.2 No-Load Stability
      3. 8.3.3 LDO1 and LDO2 Control Registers
      4. 8.3.4 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.4.1  Functional Description
        2. 8.3.4.2  Circuit Operation
        3. 8.3.4.3  PWM Operation
        4. 8.3.4.4  Internal Synchronous Rectification
        5. 8.3.4.5  Current Limiting
        6. 8.3.4.6  SW1, SW2 Operation
        7. 8.3.4.7  SW1, SW2 Control Registers
        8. 8.3.4.8  Shutdown Mode
        9. 8.3.4.9  Soft Start
        10. 8.3.4.10 Low Dropout Operation
        11. 8.3.4.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.4.12 Power-Up Sequencing Using the EN_T Function
      5. 8.3.5 Flexible Power-On Reset (for example, Power Good with Delay)
      6. 8.3.6 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
    6. 8.6 LP8731-Q1 Register Maps
      1. 8.6.1  Interrupt Status Register (ISRA) 0x02
      2. 8.6.2  System Control 1 Register (SCR1) 0x07
      3. 8.6.3  EN_DLY Preset Delay Sequence after EN_T Assertion
      4. 8.6.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) - 0x10
      5. 8.6.5  Buck and LDO Status Register (BKLDOSR) - 0x11
      6. 8.6.6  BUCK Voltage Change Control Register 1 (VCCR) - 0x20
      7. 8.6.7  BUCK1 Target Voltage 1 Register (B1TV1) - 0x23
      8. 8.6.8  BUCK1 Target Voltage 2 Register (B1TV2) - 0x24
      9. 8.6.9  BUCK1 Ramp Control Register (B1RC) - 0x25
      10. 8.6.10 BUCK2 Target 1 Register (B2TV1) - 0x29
      11. 8.6.11 BUCK2 Target 2 Register (B2TV2) - 0x2A
      12. 8.6.12 BUCK2 Ramp Control Register (B2RC) - 0x2B
      13. 8.6.13 BUCK Function Register (BFCR) - 0x38
      14. 8.6.14 Spread Spectrum Function
      15. 8.6.15 LDO1 Control Register (LDO1VCR) - 0x39
      16. 8.6.16 LDO2 Control Register (LDO2VCR) - 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
          1. 9.2.2.1.1 Inductors for SW1 and SW2
            1. 9.2.2.1.1.1 Method 1:
            2. 9.2.2.1.1.2 Method 2:
          2. 9.2.2.1.2 External Capacitors
        2. 9.2.2.2 LDO Capacitor Selection
          1. 9.2.2.2.1 Input Capacitor
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Capacitor Characteristics
          4. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.2.6 I2C Pull-up Resistor
          7. 9.2.2.2.7 Operation Without I2C Interface
        3. 9.2.2.3 Junction Temperature
      3. 9.2.3 Application Curves (LDO)
      4. 9.2.4 Application Curves (BUCK)
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Two LDOs for Powering Internal Processor Functions and I/Os
  • High-Speed Serial Interface for Independent Control of Device Functions and Settings
  • Precision Internal Reference
  • Thermal Overload Protection
  • Current Overload Protection
  • Software Programmable Regulators
  • External Power-On-Reset Function for Buck1 and Buck2 (Power Good with Delay Function)
  • Undervoltage Lockout (UVLO)
  • LP8731-Q1 is an Automotive-Grade Product: AECQ-100 Grade-1 Qualified
  • Step-Down DC/DC Converter (2xBuck)
    • Programmable VOUT from:
      • Buck1 : 0.8875 V – 1.675 V at 1.2 A
      • Buck2 : 0.8875 V – 1.675 V at 1.2 A
    • Up to 96% Efficiency
    • PWM Switching Frequency of 2.1 MHz
    • ±2% Output Voltage Accuracy
    • Automatic Soft Start
  • Linear Regulators (2xLDO)
    • Programmable VOUT of 0.8 V to 3.3 V
    • ±3% Output Voltage Accuracy
    • 300-mA Output Current
    • 30-mV (Typical) Dropout

2 Applications

  • Configurable Output PMU for ADAS (Advanced Driver Assistance Systems)
  • FPGA, DSP Core Power
  • Applications Processors

3 Description

The LP8731-Q1 is a multi-function, programmable Power Management Unit (PMU), optimized for low power FPGAs, microprocessors, and DSPs. This device integrates two highly efficient 1.2-A step-down DC-DC converters with dynamic voltage management (DVM), two 300-mA linear regulators, and a 400-kHz I2C-compatible interface to allow a host controller access to the internal control registers of the LP8731-Q1. The LP8731-Q1 device additionally features programmable power-on sequencing.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (MAX)
LP8731-Q1 DSBGA (25) 2.52 mm x 2.52 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

typapp_snvsa28.gif

4 Revision History

DATE REVISION NOTES
December 2014 * Initial release.