The OPA202, OPA2202, and OPA4202 (OPAx202) are a family of devices built on TI's industry-leading precision super-beta, complementary, bipolar semiconductor process. This process offers ultra-low flicker noise, low offset voltage, low offset voltage temperature drift, and excellent linearity with common-mode and power-supply variation. These devices offer an exceptional combination of dc precision, heavy capacitive load drive, and protection against external EMI, thermal, and short-circuit events.
The supply current is 580 µA at ±18 V. The OPAx202 do not exhibit phase inversion, and the series is stable with high capacitive loads. The OPAx202 are fully specified with a temperature range from –40°C to +105°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA202 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT-23 (5) | 2.90 mm × 1.60 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
OPA2202 | VSSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 4.90 mm × 3.91 mm | |
OPA4202 | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm |
Changes from G Revision (March 2020) to H Revision
Changes from F Revision (February 2020) to G Revision
Changes from E Revision (February 2020) to F Revision
Changes from D Revision (December 2019) to E Revision
Changes from C Revision (October 2018) to D Revision
Changes from B Revision (December 2018) to C Revision
Changes from A Revision (September 2018) to B Revision
Changes from * Revision (October 2017) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
D (SOIC)
DGK (VSSOP) |
DBV (SOT-23) | |||
–IN | 2 | 4 | I | Inverting input |
+IN | 3 | 3 | I | Noninverting input |
NC | 1, 5, 8 | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | O | Output |
V– | 4 | 2 | — | Negative (lowest) power supply |
V+ | 7 | 5 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
–IN A | 2 | I | Inverting input channel A |
+IN A | 3 | I | Noninverting input channel A |
–IN B | 6 | I | Inverting input channel B |
+IN B | 5 | I | Noninverting input channel B |
OUT A | 1 | O | Output channel A |
OUT B | 7 | O | Output channel B |
V– | 4 | — | Negative supply |
V+ | 8 | — | Positive supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
–IN A | 2 | I | Inverting input channel A |
+IN A | 3 | I | Noninverting input channel A |
–IN B | 6 | I | Inverting input channel B |
+IN B | 5 | I | Noninverting input channel B |
–IN C | 9 | I | Inverting input channel C |
+IN C | 10 | I | Noninverting input channel C |
–IN D | 13 | I | Inverting input channel D |
+IN D | 12 | I | Noninverting input channel D |
OUT A | 1 | O | Output channel A |
OUT B | 7 | O | Output channel B |
OUT C | 8 | O | Output channel C |
OUT D | 14 | O | Output channel D |
V– | 11 | — | Negative supply |
V+ | 4 | — | Positive supply |