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  • OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp

    • SBOS933I February   2019  – August 2021 OPA2990 , OPA4990 , OPA990

      PRODUCTION DATA  

  • CONTENTS
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  • OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Protection Circuitry
      2. 7.3.2  EMI Rejection
      3. 7.3.3  Thermal Protection
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Common-Mode Voltage Range
      6. 7.3.6  Phase Reversal Protection
      7. 7.3.7  Electrical Overstress
      8. 7.3.8  Overload Recovery
      9. 7.3.9  Typical Specifications and Distributions
      10. 7.3.10 Packages With an Exposed Thermal Pad
      11. 7.3.11 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High Voltage Buffered Multiplexer
      2. 8.2.2 Slew Rate Limit for Input Protection
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTE|16
    • MPQF149D
  • RUC|14
    • MPQF212D
  • PW|14
    • MPDS360A
  • D|14
    • MPDS177H
Thermal pad, mechanical data (Package|Pins)
  • RTE|16
    • QFND525B
  • RUC|14
    • QFND283A
Orderable Information
  • sbos933i_oa
  • sbos933i_pm
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DATA SHEET

OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp

1 Features

  • Low offset voltage: ±300 µV
  • Low offset voltage drift: ±0.6 µV/°C
  • Low noise: 30 nV/√Hz at 1 kHz
  • High common-mode rejection: 115 dB
  • Low bias current: ±10 pA
  • Rail-to-rail input and output
  • MUX-friendly/comparator inputs
    • Amplifier operates with differential inputs up to supply rail
    • Amplifier can be used in open-loop or as comparator
  • Wide bandwidth: 1.1-MHz GBW
  • High slew rate: 4.5 V/µs
  • Low quiescent current: 120 µA per amplifier
  • Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V
  • Robust EMIRR performance: 78 dB at 1.8 GHz
  • Differential and common-mode input voltage range to supply rail

2 Applications

  • Multiplexed data-acquisition systems
  • Test and measurement equipment
  • Motor drive: power stage and control modules
  • Power delivery: UPS, server, and merchant network power
  • ADC driver and reference buffer amplifier
  • Programmable logic controllers
  • Analog input and output modules
  • High-side and low-side current sensing
  • High precision comparator

3 Description

The OPAx990 family (OPA990, OPA2990, and OPA4990) is a family of high voltage (40 V) general purpose operational amplifiers. These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), and low offset drift (±0.6 µV/°C, typ).

Unique features such as differential and common-mode input voltage range to the supply rail, high short-circuit current (±80 mA), high slew rate (4.5 V/µs), and shutdown make the OPAx990 an extremely flexible, robust, and high-performance op amp for high-voltage industrial applications.

The OPAx990 family of op amps is available in micro-size packages (such as X2QFN, WSON, and SOT-553), as well as standard packages (such as SOT-23, SOIC, and TSSOP), and is specified from –40°C to 125°C.

Device Information
PART NUMBER(1)PACKAGEBODY SIZE (NOM)
OPA990SOT-23 (5)2.90 mm × 1.60 mm
SOT-23 (6)2.90 mm × 1.60 mm
SC70 (5)2.00 mm × 1.25 mm
SOT-553 (5)(2)1.60 mm × 1.20 mm
OPA2990SOIC (8)4.90 mm × 3.90 mm
SOT-23 (8)2.90 mm × 1.60 mm
TSSOP (8)3.00 mm × 4.40 mm
VSSOP (8)3.00 mm × 3.00 mm
VSSOP (10) 3.00 mm × 3.00 mm
WSON (8)2.00 mm × 2.00 mm
X2QFN (10)2.00 mm × 1.50 mm
OPA4990SOIC (14)8.65 mm × 3.90 mm
TSSOP (14)5.00 mm × 4.40 mm
WQFN (16)3.00 mm × 3.00 mm
X2QFN (14)2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) This package is preview only.
GUID-C3672468-12C0-4DED-AF40-45D0B86E2B9A-low.gif OPAx990 in a High-Voltage, Multiplexed, Data-Acquisition System

4 Revision History

Changes from Revision H (May 2021) to Revision I (August 2021)

  • Removed preview notation from OPA2990 VSSOP-8 package (DGK) from Device Information tableGo
  • Removed preview notation from OPA2990 VSSOP-8 package (DGK) in the Pin Configuration and Functions sectionGo
  • Added note explaining difference between DDF and TDDF packages in the Pin Configuration and Functions sectionGo
  • Corrected typo describing shutdown region in Recommended Operating Conditions to match rest of data sheetGo
  • Changed Junction-to-ambient thermal resistance value for SOT-23-6 (DBV-6) from 1174.5ºC/W to 174.5ºC/W in the Thermal Information for Single Channel section.Go
  • Added clarifying statement regarding logic low signal for SHDN pin in the Shutdown sectionGo
  • Corrected statement on shutdown enable and disable times in the Shutdown section from 30 µs and 3 µs to 11 µs and 2.5 µs, respectively, to match the Electrical Characteristics sectionGo

Changes from Revision G (December 2020) to Revision H (May 2021)

  • Removed preview notation from OPA4990 WQFN (16) package from Device Information tableGo
  • Removed preview notation from OPA4990 X2QFN (14) package from Device Information tableGo
  • Removed preview notation from OPA4990 and OPA4990S RTE package (WQFN) in the Pin Configuration and Functions sectionGo
  • Removed Table of Graphs from Specifications sectionGo
  • Clarified threshold and maximum voltage levels of the shutdown pin in the Shutdown sectionGo
  • Removed Related Links from Device and Documentation sectionGo

Changes from Revision F (May 2020) to Revision G (December 2020)

  • Updated the numbering format for tables, figures and cross-references throughout the document Go
  • Removed preview notation from OPA2990 SOT-23 (8) package from Device Information tableGo
  • Added OPA2990 VSSOP (10) package to Device Information tableGo
  • Clarified SHDN notation on OPA990S Pin Functions Go
  • Removed preview notation from OPA2990 DDF package (SOT-23) in the Pin Configuration and Functions sectionGo
  • Removed preview notation from OPA2990S DGS package (VSSOP) in the Pin Configuration and Functions section Go
  • Clarified SHDN notation for OPA2990S in the Pin Functions section Go
  • Clarified SHDN notation for OPA4990S in the Pin Functions section Go

Changes from Revision E (December 2019) to Revision F (May 2020)

  • Removed preview notation from OPA2990 X2QFN (10) package from Device Information table Go
  • Removed preview notation from OPA2990S RUG package (X2QFN) in the Pin Configuration and Functions section Go
  • Changed RUG (X2QFN) in Thermal Information for Dual Channel sectionGo

Changes from Revision D (July 2019) to Revision E (December 2019)

  • Changed the OPA990 and OPA4990 device statuses from Advance Information to Production Data Go
  • Removed preview notation from OPA990 SOT-23 (5) package from Device Information tableGo
  • Removed preview notation from OPA990S SOT-23 (6) package from Device Information tableGo
  • Removed preview notation from OPA990 SC70 (5) package from Device Information tableGo
  • Removed preview notation from OPA4990 SOIC (14) package from Device Information tableGo
  • Removed preview notation from OPA4990 TSSOP (14) package from Device Information tableGo
  • Removed preview notation from OPA990 DBV package (SOT-23) in the Pin Configuration and Functions sectionGo
  • Removed preview notation from OPA990 DCK package (SC70) in the Pin Configuration and Functions sectionGo
  • Removed preview notation from OPA4990 D (SOIC) and TSSOP (PW) packages in the Pin Configuration and Functions sectionGo
  • Removed preview notation from OPA990S DBV package (SOT-23) in the Pin Configuration and Functions sectionGo

Changes from Revision C (May 2019) to Revision D (July 2019)

  • Removed preview notation from OPA2990 WSON (8) package from Device Information tableGo
  • Removed preview notation from OPA2990 DSG package (WSON) in the Pin Configuration and Functions sectionGo
  • Added SHUTDOWN to Electrical Characteristics tableGo
  • Added Shutdown section to the Detailed Description sectionGo

Changes from Revision B (April 2019) to Revision C (May 2019)

  • Removed preview notation from OPA2990 TSSOP (8) package from Device Information tableGo
  • Removed preview notation from OPA2990 PW package (TSSOP) in the Pin Configuration and Functions sectionGo

Changes from Revision A (March 2019) to Revision B (April 2019)

  • Removed preview notation from OPA2990 SOIC (8) package from Device Information tableGo
  • Removed preview notation from OPA2990 D package (SOIC) in the Pin Configuration and Functions sectionGo

Changes from Revision * (February 2019) to Revision A (March 2019)

  • Changed the OPA2990 device status from Advance Information to Production Data Go

5 Pin Configuration and Functions

DRL package is preview only.
Figure 5-1 OPA990 DBV and DRL Package(A)
5-Pin SOT-23 and SOT-553
Top View
Figure 5-2 OPA990 DCK Package
5-Pin SC70
Top View
Table 5-1 Pin Functions: OPA990
PIN I/O DESCRIPTION
NAME DBV and DRL DCK
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
GUID-20200923-CA0I-Z4RZ-SS1N-83VSKFFBBLKF-low.gif
DRL package is preview only.
Figure 5-3 OPA990S DBV and DRL Package(A)
6-Pin SOT-23 and SOT-563
Top View
Table 5-2 Pin Functions: OPA990S
PIN I/O DESCRIPTION
NAME NO.
IN+ 3 I Noninverting input
IN– 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information.
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply
DDF and TDDF differ in pin 1 orientation within tape and reel. See Mechanical, Packaging, and Orderable Information section for more information.
Figure 5-4 OPA2990 D, DDF, DGK, PW, and TDDF Package(A)
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information.
Figure 5-5 OPA2990 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3 Pin Functions: OPA2990
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-20200923-CA0I-PDLJ-ZGRX-JK959RBXDZK1-low.gifFigure 5-6 OPA2990S DGS Package
10-Pin VSSOP
Top View
GUID-20200923-CA0I-GKL7-PBSM-D9N0XW3ZL1HM-low.gifFigure 5-7 OPA2990S RUG Package
10-Pin X2QFN
Top View
Table 5-4 Pin Functions: OPA2990S
PIN I/O DESCRIPTION
NAME VSSOP X2QFN
IN1+ 3 10 I Noninverting input, channel 1
IN1– 2 9 I Inverting input, channel 1
IN2+ 7 4 I Noninverting input, channel 2
IN2– 8 5 I Inverting input, channel 2
OUT1 1 8 O Output, channel 1
OUT2 9 6 O Output, channel 2
SHDN1 5 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information.
SHDN2 6 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Shutdown section for more information.
V+ 10 7 — Positive (highest) power supply
V– 4 1 — Negative (lowest) power supply
Figure 5-8 OPA4990 D and PW Package
14-Pin SOIC and TSSOP
Top View
Figure 5-10 OPA4990 RUC Package
14-Pin X2QFN With Exposed Thermal Pad
Top View
Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information.
Figure 5-9 OPA4990 RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-5 Pin Functions: OPA4990
PIN I/O DESCRIPTION
NAME SOIC and TSSOP WQFN X2QFN
IN1+ 3 1 2 I Noninverting input, channel 1
IN1– 2 16 1 I Inverting input, channel 1
IN2+ 5 3 4 I Noninverting input, channel 2
IN2– 6 4 5 I Inverting input, channel 2
IN3+ 10 10 9 I Noninverting input, channel 3
IN3– 9 9 8 I Inverting input, channel 3
IN4+ 12 12 11 I Noninverting input, channel 4
IN4– 13 13 12 I Inverting input, channel 4
NC — 6, 7 — — Do not connect
OUT1 1 15 14 O Output, channel 1
OUT2 7 5 6 O Output, channel 2
OUT3 8 8 7 O Output, channel 3
OUT4 14 14 13 O Output, channel 4
V+ 4 2 3 — Positive (highest) power supply
V– 11 11 10 — Negative (lowest) power supply
GUID-20200923-CA0I-3L20-RHTV-T0F2CP0GF1JS-low.gif
Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information.
Figure 5-11 OPA4990S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6 Pin Functions: OPA4990S
PIN I/O DESCRIPTION
NAME NO.
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
IN2+ 3 I Noninverting input, channel 2
IN2– 4 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 15 O Output, channel 1
OUT2 5 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
SHDN12 6 I Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers disabled. See Shutdown section for more information.
SHDN34 7 I Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers disabled. See Shutdown section for more information.
VCC+ 2 — Positive (highest) power supply
VCC– 11 — Negative (lowest) power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 0 42 V
Signal input pins Common-mode voltage(3) (V–) – 0.5 (V+) + 0.5 V
Differential voltage(3) VS + 0.2 V
Current(3) –10 10 mA
Shutdown pin voltage(4) V– (V–) + 20 V
Output short-circuit(2) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction. See the Thermal Protection section for more information.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(4) Cannot exceed V+.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage, (V+) – (V–) 2.7 40 V
VI Input voltage range (V–) – 0.2 (V+) + 0.2 V
VIH High level input voltage at shutdown pin (amplifier disabled) (V–) + 1.1 (V–) + 20 V(1) V
VIL Low level input voltage at shutdown pin (amplifier enabled) (V–) (V–) + 0.2 V
TA Specified temperature –40 125 °C
(1) Cannot exceed V+.

6.4 Thermal Information for Single Channel

THERMAL METRIC(1) OPA990, OPA990S UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DRL(2)
(SOT-553)
5 PINS 6 PINS 5 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 192.1 174.5 204.6 TBD TBD °C/W
RθJC(top) Junction-to-case (top) thermal resistance 113.6 113.4 116.5 TBD TBD °C/W
RθJB Junction-to-board thermal resistance 60.5 55.8 51.8 TBD TBD °C/W
ψJT Junction-to-top characterization parameter 37.2 39.6 24.9 TBD TBD °C/W
ψJB Junction-to-board characterization parameter 60.3 55.6 51.5 TBD TBD °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A TBD TBD °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) This package option is preview for OPA990.

6.5 Thermal Information for Dual Channel

THERMAL METRIC(1) OPA2990, OPA2990S UNIT
D
(SOIC)		 DDF
(SOT-23-8)		 DGK
(VSSOP)		 DGS
(VSSOP)		 DSG
(WSON)		 PW
(TSSOP)		 RUG
(X2QFN)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 138.7 150.4 189.3 152.2 81.6 188.4 149.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78.7 85.6 75.8 67.3 101.6 77.1 58.3 °C/W
RθJB Junction-to-board thermal resistance 82.2
70.0

 111.0 95.5 48.3 119.1 77.7 °C/W
ψJT Junction-to-top characterization parameter 27.8 8.1 15.4 67.9 6.0 14.2 1.3 °C/W
ψJB Junction-to-board characterization parameter 81.4 69.6 109.3 94.3 48.3 117.4 77.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 22.8 N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Thermal Information for Quad Channel

THERMAL METRIC(1) OPA4990, OPA4990S UNIT
D
(SOIC)		 PW
(TSSOP)		 RTE(2)
(WQFN)		 RUC
(WQFN)
14 PINS 14 PINS 16 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 105.2 134.7 53.5 143.0    °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.2 55.0 58.3 46.4    °C/W
RθJB Junction-to-board thermal resistance 61.1 79.0 28.6 81.8    °C/W
ψJT Junction-to-top characterization parameter 21.4 9.2 2.1 1.0    °C/W
ψJB Junction-to-board characterization parameter 60.7 78.1 28.6 81.5    °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 12.6 N/A    °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) This package option is preview for OPA4990.

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.3 ±1.5 mV
TA = –40°C to 125°C ±1.75
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.6 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 4 V to 40 V TA = –40°C to 125°C ±0.1 ±1.3 µV/V
VCM = V–, VS = 2.7 V to 40 V(2) ±0.75 ±6.6
Channel separation f = 0 Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±5 pA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   6 µVPP
  1   µVRMS
eN Input voltage noise density f = 1 kHz 30   nV/√Hz
f = 10 kHz   28  
iN Input current noise f = 1 kHz   2   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 40 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair) TA = –40°C to 125°C 100 115 dB
VS = 4 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair) 75 90
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 2 V (PMOS pair)(2) 70 90
VS = 2.7 – 40 V, (V+) – 1 V < VCM < (V+) + 0.1 V (NMOS pair) 80
(V+) – 2 V < VCM < (V+) – 1 V See Offset Voltage (Transition Region) in the Typical Characteristics section
INPUT CAPACITANCE
ZID Differential 540 || 3 GΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V		 120 145 dB
TA = –40°C to 125°C 142
VS = 4 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V		 104 130
TA = –40°C to 125°C 125
VS = 2.7 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V(2) 		101 118 dB
TA = –40°C to 125°C 117 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1.1 MHz
SR Slew rate VS = 40 V, G = +1, CL = 20 pF 4.5 V/μs
tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 4 µs
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 2
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 5
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 3
Phase margin G = +1, RL = 10 kΩ, CL = 20 pF 60 °
Overload recovery time VIN  × gain > VS 600 ns
THD+N Total harmonic distortion + noise VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz 0.00162%
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 40 V, RL = no load   2 mV
VS = 40 V, RL = 10 kΩ   45 60
VS = 40 V, RL = 2 kΩ   200 300
VS = 2.7 V, RL = no load   1
VS = 2.7 V, RL = 10 kΩ   5 20
VS = 2.7 V, RL = 2 kΩ   25 50
ISC Short-circuit current ±80 mA
CLOAD Capacitive load drive See Small-Signal Overshoot vs Capacitive Load in the Typical Characteristics section
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 575 Ω
POWER SUPPLY
IQ Quiescent current per amplifier OPA2990, OPA4990, IO = 0 A 120 150 µA
TA = –40°C to 125°C 160
OPA990, IO = 0 A 130 170
TA = –40°C to 125°C 175
Turn-on time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
 40 μs
SHUTDOWN
IQSD Quiescent current per amplifier VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V 20 30 µA
ZSHDN Output impedance during shutdown VS = 2.7 V to 40 V, amplifier disabled, SHDN = V– + 2 V 10 || 12 GΩ || pF
VIH Logic high threshold voltage (amplifier disabled) For valid input high, the SHDN pin voltage should be greater than the maximum threshold but less than or equal to (V–) + 20 V (V–) + 0.8 (V–) + 1.1 V
VIL Logic low threshold voltage (amplifier enabled) For valid input low, the SHDN pin voltage should be less than the minimum threshold but greater than or equal to V– (V–) + 0.2 (V–) + 0.8 V
tON Amplifier enable time (1) G = +1, VCM = V–, VO = 0.1 × VS / 2 11 µs
tOFF Amplifier disable time (1) VCM = V–, VO = VS / 2  2.5 µs
SHDN pin input bias current (per pin) VS = 2.7 V to 40 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V 500 nA
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150
(1) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(2) Specified by characterization only.

 
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