OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier
- SBOS376I November 2006 – July 2016 OPA827
  
  PRODUCTION DATA.

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DATA SHEET

OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier

1 Features

Input Voltage Noise Density:
4 nV/√Hz at 1 kHz
Input Voltage Noise:
0.1 Hz to 10 Hz: 250 nV_PP
Input Bias Current: 10 pA (Maximum)
Input Offset Voltage: 150 µV (Maximum)
Input Offset Drift: 2 µV/°C (Maximum)
Gain Bandwidth: 22 MHz
Slew Rate: 28 V/µs
Quiescent Current: 4.8 mA/Ch
Wide Supply Range: ±4 V to ±18 V
Packages: 8-Pin SOIC and 8-Pin VSSOP

2 Applications

ADC Drivers
DAC Output Buffers
Test Equipment
Medical Equipment
PLL Filters
Seismic Applications
Transimpedance Amplifiers
Integrators
Active Filters

3 Description

The OPA827 series of JFET operational amplifiers combine outstanding DC precision with excellent AC performance. These amplifiers offer low offset voltage (150 µV, maximum), very low drift over temperature (0.5 µV/°C, typical), low-bias current (3 pA, typical), and very low 0.1-Hz to 10-Hz noise (250 nV_PP, typical). The device operates over a wide supply voltage range, ±4 V to ±18 V on a low supply current (4.8 mA/Ch, typical).

Excellent AC characteristics, such as a 22-MHz gain bandwidth product (GBW), a slew rate of 28 V/µs, and precision DC characteristics make the OPA827 series well-suited for a wide range of applications including 16-bit to 18-bit mixed signal systems, transimpedance (I/V-conversion) amplifiers, filters, precision ±10-V front ends, and professional audio applications.

The OPA827 is available in both 8-pin SOIC and 8-pin VSSOP surface-mount packages, and is specified from –40°C to 125°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
OPA827	SOIC (8)	4.90 mm × 3.91 mm
OPA827	VSSOP (8)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Input Voltage Noise Density vs Frequency

0.1-Hz to 10-Hz Noise

4 Revision History

Changes from H Revision (May 2012) to I Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Deleted Package/Ordering Information table, see POA at the end of the data sheetGo
Changed values in the Thermal Information table to align with JEDEC standardsGo

Changes from G Revision (February 2012) to H Revision

Updated Figure 3Go
Updated Figure 4Go

Changes from F Revision (March 2009) to G Revision

Changed Input bias current and Input offset drift Features bulletsGo
Changed product status from Mixed Status to Production DataGo
Changed description of amplifier drift and bias current in first paragraph of Description sectionGo
Deleted high grade (OPA827I) option and footnote 2 from Package/Ordering Information tableGo
Deleted high grade (OPA827I) option from Electrical Characteristics tableGo
Changed Offset Voltage, Input Offset Voltage Drift parameter typical and maximum specifications in Electrical Characteristics tableGo
Changed Input Bias Current section specifications in Electrical Characteristics tableGo
Changed -40°C to +85°C Input Bias Current parameter unitGo
Added Frequency Response, Slew Rate parameter minimum specification to Electrical Characteristics tableGo
Added Output, Short-Circuit Current parameter minimum specification to Electrical Characteristics tableGo
Updated Figure 7Go
Updated Figure 8Go
Updated Figure 9Go
Updated Figure 11Go
Updated Figure 12Go
Updated Figure 14Go

5 Pin Configuration and Functions

D and DGK Packages

8-Pin SOIC and VSSOP

Top View

1. NC denotes no internal connection.

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
+IN	3	I	Noninverting input
–IN	2	I	Inverting input
NC	1, 5, 8	—	No internal connection (can be left floating)
OUT	6	O	Output
V+	7	—	Positive power supply
V–	4	—	Negative power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_S = (V+) – (V–)		40	V
Input voltage⁽²⁾	(V–) – 0.5	(V+) + 0.5	V
Input current⁽²⁾		±10	mA
Differential input voltage		±V_S	V
Output short-circuit⁽³⁾	Continuous
Operating temperature, T_A	–55	150	°C
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current-limited to 10 mA or less.

(3) Short-circuit to V_S/2 (ground in symmetrical dual-supply setups).

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_S	Supply voltage	±4		±18	V
T_A	Specified temperature	–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		OPA827		UNIT
		D (SOIC)	DGK (VSSOP)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	160	180	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	75	55	°C/W
R_θJB	Junction-to-board thermal resistance	60	130	°C/W
ψ_JT	Junction-to-top characterization parameter	9	—	°C/W
ψ_JB	Junction-to-board characterization parameter	50	120	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at V_S = ±4 V to ±18 V, T_A = 25°C, R_L = 10 kΩ connected to midsupply, and V_CM = V_OUT = midsupply (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OFFSET VOLTAGE
V_OS	Input offset voltage	V_S = ±15 V, V_CM = 0 V		75	150	µV
dV_OS/dT	Input offset voltage drift	T_A = –40°C to 125°C		0.1	2	µV/°C
PSRR	Input offset voltage vs power supply			0.2	1	µV/V
PSRR	Input offset voltage vs power supply	T_A = –40°C to 125°C			3	µV/V
INPUT BIAS CURRENT
I_B	Input bias current			±3	±10	pA
		T_A = –40°C to 85°C			±500	pA
		T_A = –40°C to 125°C			±5	nA
I_OS	Input Offset Current			±3	±10	pA
NOISE
e_n	Input Voltage Noise:	f = 0.1 Hz to 10 Hz, V_S = ±18 V, V_CM = 0 V		250		nV_PP
	Input Voltage Noise Density	f = 1 kHz, V_S = ±18 V, V_CM = 0 V		4		nV/√Hz
	Input Voltage Noise Density	f = 10 kHz, V_S = ±18 V, V_CM = 0 V		3.8		nV/√Hz
i_n	Input current noise density	f = 1 kHz, V_S = ±18 V, V_CM = 0 V		2.2		fA/√Hz
INPUT VOLTAGE RANGE
V_CM	Common-mode voltage range		(V–) + 3		(V+) – 3	V
CMRR	Common-mode rejection ratio	(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S < 10 V	104	114		dB
		(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S ≥ 10 V	114	126
		(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S < 10 V T_A = –40°C to 125°C	100
		(V−) + 3 V ≤ V_CM ≤ (V+) − 3 V, V_S ≥ 10 V T_A = –40°C to 125°C	110
INPUT IMPEDANCE
Differential				10¹³ ∥ 9		Ω ∥ pF
Common-mode				10¹³ ∥ 9		Ω ∥ pF
OPEN-LOOP GAIN
A_OL	Open-loop voltage gain	(V–) + 3 V ≤ V_O ≤ (V+) – 3 V, R_L = 1 kΩ	120	126		dB
A_OL	Open-loop voltage gain	(V–) + 3 V ≤ V_O ≤ (V+) – 3 V, R_L = 1 kΩ T_A = –40°C to 125°C	114			dB
FREQUENCY RESPONSE
GBW	Gain-bandwidth product	G = +1		22		MHz
SR	Slew rate	G = –1	20	28		V/µs
t_S	Settling time	±0.01%, 10-V step, G = –1, C_L = 100 pF		550		ns
t_S	Settling time	0.00075% (16-bit), 10-V step, G = –1, C_L = 100 pF		850		ns
	Overload recovery time	Gain = –10		150		ns
THD+N	Total Harmonic Distortion + Noise	G = +1, f = 1 kHz		0.00004%
THD+N	Total Harmonic Distortion + Noise	V_O = 3 V_RMS, R_L = 600 Ω		–128		dB
OUTPUT
	Voltage output swing	R_L = 1 kΩ, A_OL > 120 dB	(V–) + 3		(V+) – 3	V
	Voltage output swing	R_L = 1 kΩ, A_OL > 114 dB T_A = –40°C to 125°C	(V–) + 3		(V+) – 3	V
I_OUT	Output current	\|V_S – V_OUT\| < 3 V		30		mA
I_SC	Short-circuit current		±55	±65		mA
C_LOAD	Capacitive load drive		See Typical Characteristics
Z_O	Open-loop output impedance		See Typical Characteristics
POWER SUPPLY
V_S	Specified voltage		±4		±18	V
I_Q	Quiescent current (per amplifier)	I_OUT = 0A		4.8	5.2	mA
I_Q	Quiescent current (per amplifier)	T_A = –40°C to 125°C			6	mA

6.6 Typical Characteristics

At T_A = 25°C, V_S = ±18 V, R_L = 10 kΩ connected to midsupply, and V_CM = V_OUT = midsupply, unless otherwise noted.

Figure 1. Input Voltage Noise Density vs Frequency

Figure 3. Total Harmonic Distortion + Noise Ratio
vs Frequency

Figure 5. 0.1-Hz to 10-Hz Noise

Figure 7. Offset Voltage Drift Production Distribution

Figure 9. Offset Voltage vs Common-Mode Voltage

Figure 11. Offset Voltage vs Temperature

Figure 13. Input Bias Current vs Common-Mode Voltage

Figure 15. Normalized Quiescent Current vs Time

Figure 17. Quiescent Current vs Supply Voltage

Figure 19. Output Voltage Swing vs Output Current

Figure 21. Common-Mode Rejection Ratio vs Frequency

Figure 23. Common-Mode Rejection Ratio vs Temperature

Figure 25. Closed-Loop Gain vs Frequency

Figure 27. Open-Loop Output Impedance vs Frequency

Figure 29. No Phase Reversal

Figure 31. Negative Overload Recovery

Figure 33. Small-Signal Step Response

Figure 35. Large-Signal Step Response

10 V_PP, C_L = 10 pF

Figure 37. Large-Signal Positive Settling Time

10 V_PP, C_L = 10 pF

Figure 39. Large-Signal Negative Settling Time

Figure 2. Integrated Input Voltage Noise vs Bandwidth

Figure 4. Total Harmonic Distortion + Noise Ratio
vs Amplitude

Figure 6. Offset Voltage Production Distribution

Figure 8. Offset Voltage vs Common-Mode Voltage

Figure 10. V_OS Warmup

Figure 12. Input Bias Current and Offset Current
vs Supply Voltage

Figure 14. Input Bias Current vs Temperature

Figure 16. Quiescent Current vs Temperature

Figure 18. Output Voltage Swing vs Output Current

Figure 20. Power-Supply Rejection Ratio vs Frequency

Figure 22. Power-Supply Rejection Ratio vs Temperature

Figure 24. Open-Loop Gain and Phase vs Frequency

Figure 26. Open-Loop Gain vs Temperature

Figure 28. Small-Signal Overshoot vs Capacitive Load

Figure 30. Positive Overload Recovery

Figure 32. Small-Signal Step Response

Figure 34. Large-Signal Step Response

10 V_PP, C_L = 100 pF

Figure 36. Large-Signal Positive Settling Time

10 V_PP, C_L = 100 pF

Figure 38. Large-Signal Negative Settling Time

Figure 40. Short-Circuit Current vs Temperature