SLAS759B August   2012  – January 2016 PCM5141 , PCM5142

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SCK Input
    7. 7.7  Timing Requirements: PCM Audio Data
      1. 7.7.1 Timing Requirements: I2S Master
    8. 7.8  Timing Requirements: XSMT
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1 PCM514x Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2 Interpolation Filter
        3. 8.3.4.3 Fixed Audio Processing Flow (Program 5)
          1. 8.3.4.3.1 Processing Blocks - Detailed Descriptions
          2. 8.3.4.3.2 Biquad Section
          3. 8.3.4.3.3 Dynamic Range Compression
          4. 8.3.4.3.4 Stereo Mixer
          5. 8.3.4.3.5 Stereo Multiplexer
          6. 8.3.4.3.6 Mono Mixer
          7. 8.3.4.3.7 Master Volume Control
          8. 8.3.4.3.8 Miscellaneous Coefficients
      5. 8.3.5 DAC Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Recommended Output Filter for the PCM514x
        3. 8.3.5.3 Choosing Between VREF and VCOM Modes
          1. 8.3.5.3.1 Voltage Reference and Output Levels
          2. 8.3.5.3.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        4. 8.3.5.4 Digital Volume Control
          1. 8.3.5.4.1 Emergency Ramp-Down
        5. 8.3.5.5 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM514x Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.5.2 Power Save Modes
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Register Maps
    1. 12.1 PCM514x Register Map
      1. 12.1.1 Detailed Register Descriptions
        1. 12.1.1.1 Register Map Summary
        2. 12.1.1.2 Page 0 Registers
        3. 12.1.1.3 Page 1 Registers
        4. 12.1.1.4 Page 44 Registers
        5. 12.1.1.5 Page 253 Registers
      2. 12.1.2 PLL Tables for Software Controlled Devices
      3. 12.1.3 Coefficient Data Formats
      4. 12.1.4 Power Down and Reset Behavior
  13. 13Device and Documentation Support
    1. 13.1 Development Support
    2. 13.2 Documentation Support
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Programmable miniDSP
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR
  • Integrated High-Performance Audio PLL With BCK Reference To Generate SCK Internally
  • Accepts 16-, 20-, 24-, And 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified, Right-Justified, TDM / DSP
  • SPI or I2C Control
  • Software or Hardware Configuration
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated
  • 1.8-V or 3.3-V Fail-Safe LVCMOS Digital Inputs
  • Single Supply Operation:
    3.3-V Analog, 1.8-V or 3.3-V Digital
  • Integrated Power-On Reset
  • Small 28-pin TSSOP Package

2 Applications

  • A/V Receivers
  • DVD, BD Players
  • HDTV Receivers
  • Applications Requiring 2-VRMS Audio Output

3 Description

The PCM514x devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM514x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Members of the PCM514x family integrate a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators, and other differentiating features to their products.

The PCM514x provides 2.1-VRMS ground centered outputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ, allowing the PCM514x to drive up to 10 products in parallel, such as LCD TV, DVDR, and AV receivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Device Information

DEVICE NAME PACKAGE BODY SIZE (NOM)
PCM5141 TSSOP (28) 9.70 mm × 4.40 mm
PCM5142

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Simplified System Diagram

PCM5141 PCM5142 pcm1865_pcm514x_tpa3130_tpa6120a2_sysdiag.gif