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SN74AHCT165 8-Bit Parallel-Load Shift Register with TTL-Compatible Inputs
- SCLS989 November 2023 SN74AHCT165
  
  PRODUCTION DATA

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SN74AHCT165 8-Bit Parallel-Load Shift Register with TTL-Compatible Inputs

1
1 Features
2 Applications
3 Description
4 Pin Configuration and Functions
5 Specifications
6 Parameter Measurement Information
7 Detailed Description
8 Application and Implementation
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PW|16

Thermal pad, mechanical data (Package|Pins)

Orderable Information

scls989_oa
scls989_pm

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Data Sheet

SN74AHCT165 8-Bit Parallel-Load Shift Register with TTL-Compatible Inputs

1 Features

Operating range 4.5-V to 5.5-V V_CC
TTL-Compatible inputs
Low delay, 7 ns (25 °C, 5 V)
Latch-up performance exceeds 250 mA
per JESD 17

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