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  • SN74LS29x Programmable Frequency Dividers and Digital Timers

    • SDLS153A January   1981  – January 2016 SN74LS292 , SN74LS294

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • SN74LS29x Programmable Frequency Dividers and Digital Timers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Logic Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • N|16
    • MPDI002C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sdls153a_oa
  • sdls153a_pm
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    • Full reading width
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DATA SHEET

SN74LS29x Programmable Frequency Dividers and Digital Timers

1 Features

  • Count Divider Chain
  • Digitally Programmable from 22 to 2n
    (n = 31 for SN74LS292 , n = 15 for SN74LS294)
  • Useable Frequency Range from DC to 30 MHz
  • Easily Expandable

2 Applications

  • Frequency Division
  • Digital Timing

3 Description

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating (see Table 1).

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210 gives a period of 1.024 ms, 220 gives a period of 1.05 sec, 226 gives a period of 1.12 min, and 231 gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LS292N PDIP (16) 6.35 mm × 19.30 mm
SN74LS294N
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Symbols

SN74LS292 SN74LS294 logic_symbol_01_SDLS153.gif

4 Revision History

Changes from * Revision (January 1981) to A Revision

  • Removed SN54LS292 and SN54LS294 from the data sheetGo
  • Added ESD Ratings and Thermal Information tables, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Pin Configuration and Functions

SN74LS29x J, W, or N Package
16-Pin PDIP
Top View
SN74LS292 SN74LS294 pinout_01_SDLS153.gif

Pin Functions, SN74LS292

PIN I/O DESCRIPTION
NAME PDIP
A 10 I Programming input A
B 1 I Programming input B
C 15 I Programming input C
CLK1 4 I Clock 1 input
CLK2 5 I Clock 2 input
CLR 11 I Active-low clear input
D 14 I Programming input D
E 2 I Programming input E
GND 8 - Ground
NC 9, 12 - No connect
Q 7 O Q Output
TP — O Test Point
TP1 3 O Test Point
TP2 6 O Test Point
TP3 13 O Test Point
VCC 16 - Power

Pin Functions, SN74LS294

PIN I/O DESCRIPTION
NAME PDIP
A 2 I Programming input A
B 1 I Programming input B
C 15 I Programming input C
CLK1 4 I Clock 1 input
CLK2 5 I Clock 2 input
CLR 11 I Active-low clear input
D 14 I Programming input D
E — I Programming input E
GND 8 - Ground
NC 6, 9 ,10, 12, 13 - No connect
Q 7 O Q Output
TP 3 O Test Point
TP1 — O Test Point
TP2 — O Test Point
TP3 — O Test Point
VCC 16 - Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC(2) Supply voltage 7 V
Input voltage 7 V
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to network ground terminal.

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current (Q only) –1.2 mA
IOL Low-level output current (Q only) 24 mA
fclock Clock frequency 0 30 MHz
tw Duration of clock input pulse 16 ns
tw Duration of clear pulse SN74LS292 55 ns
SN74LS294 35
tsu Clear inactive-state set-up time 15 ns
TA Operating free-air temperature 0 70 °C

6.3 Thermal Information

THERMAL METRIC(1) SN74LS292 UNIT
N (PDIP)
16 PINS
RθJA Junction-to-ambient thermal resistance 36.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.2 °C/W
RθJB Junction-to-board thermal resistance 17.0 °C/W
ψJT Junction-to-top characterization parameter 7.0 °C/W
ψJB Junction-to-board characterization parameter 16.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT
VIK VCC = MIN, II = –18 mA –1.5 V
VOH Q VCC = MIN, VIH = 2 V, IOH = –1.2 mA, VIL = MAX 2.4 3.4 V
VOL Q VCC = MIN, VIH = 2 V, VIL = MAX IOL = 12 mA 0.25 0.4 V
IOL = 24 mA 0.35 0.5
TP(3) IOL = 0.5 mA 0.25 0.4
II VCC = MAX, VI = 7 V 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 mA
IIL CLK1, CLK2 VCC = MAX, VI = 0.4 V –0.8 mA
All others VCC = MAX, VI = 0.4 V –0.4
IOS(4) Q VCC = MAX –30 –130 mA
ICC SN74LS292 VCC = MAX, all inputs grounded, all outputs open 40 75 mA
SN74LS294 VCC = MAX, all inputs grounded, all outputs open 30 50
(1) For conditions shown as MIN or MAX, use the appropriate value specified under Recommended Operating Conditions.
(2) All typical values are at VCC = 5 V, TA = 25°C.
(3) The TP output or outputs are not intended to drive external loads, but are solely provided for test points.
(4) The duration of the short-circuit should not exceed one second.

6.5 Switching Characteristics

VCC = 5 V, TA = 25°C, RL = 667 Ω, CL = 45 pF (see Figure 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fmax From CLK1 or 2 30 50 MHz
tPLH From CLK1 or 2, to Q; Modulo set at 22, A through # = LLLHL (xxxxLS292), A through D = LLHL (xxxxLS294) 55 90 ns
tPHL From CLK1 or 2, to Q; Modulo set at 22, A through # = LLLHL (xxxxLS292), A through D = LLHL (xxxxLS294) 80 120 ns
From CLR, to Q SN74LS292 85 130
SN74LS294 35 65
SN74LS292 SN74LS294 switching_loads_SDLS153.gif Figure 1. Switching Loads
SN74LS292 SN74LS294 timing_diagram_SDLS153.gif Figure 2. Timing Diagram

6.6 Typical Characteristics

SN74LS292 SN74LS294 typicalcharvol.gif Figure 3. VOL vs IOL

 
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