Refer to the PDF data sheet for device specific package drawings
AEC-Q100 qualified for automotive applications:
The SN74LV1T04-Q1 contains a single inverter gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) | BODY SIZE (NOM)(3) |
---|---|---|---|
SN74LV1T04-Q1 | DCK (SC70, 5) | 2 mm × 2.1 mm | 2 mm × 1.25 mm |
DBV (SOT-23, 5) | 2.9 mm × 2.8 mm | 2.9 mm × 1.6 mm |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
NC | 1 | – | No connect. Not internally connected. |
A | 2 | I | Input |
GND | 3 | G | Ground |
Y | 4 | O | Output |
VCC | 5 | P | Power Supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 7 | V | |
VI | Input voltage range | -0.5 | 7 | V | |
VO | Output voltage range | -0.5 | VCC + 0.5 | V | |
VO | Voltage range applied to any output in the high-impedance or power-off state | -0.5 | 4.6 | V | |
IIK | Input clamp current(2) | VI < 0 or VI > VCC | –20 | 20 | mA |
IOK | Output clamp current(2) | VO < 0 or VO > VCC | –20 | 20 | mA |
IO | Continuous output current | VO = 0 to VCC | –25 | 25 | mA |
IO | Continuous output current through VCC or GND | –50 | 50 | mA | |
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002 (1) HBM ESD Classification Level 2 | ±2000 | V |
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B | ±1000 |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VCC | Supply voltage | 1.6 | 5.5 | V | |
VI | Input voltage | 0 | 5.5 | V | |
VO | Output voltage | 0 | VCC | V | |
VIH | High-level input voltage | VCC = 1.65V to 2V | 1.1 | V | |
VCC = 2.25V to 2.75V | 1.28 | V | |||
VCC = 3V to 3.6V | 1.45 | V | |||
VCC = 4.5V to 5.5V | 2.00 | V | |||
VIL | Low-Level input voltage | VCC = 1.65V to 2V | 0.50 | V | |
VCC = 2.25V to 2.75V | 0.65 | V | |||
VCC = 3V to 3.6V | 0.75 | V | |||
VCC = 4.5V to 5.5V | 0.85 | V | |||
IO | Output current | VCC = 1.6V to 2V | ±3 | mA | |
VCC = 2.25V to 2.75V | ±7 | mA | |||
VCC = 3.3V to 5.0V | ±15 | mA | |||
Δt/Δv | Input transition rise or fall rate | VCC = 1.6V to 5.0V | 20 | ns/V | |
TA | Operating free-air temperature | -40 | 125 | C |
THERMAL METRIC(1) | SN74LV1T04-Q1 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23) | DCK (SC70) | |||
5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 278.0 | 293.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 180.5 | 208.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 184.4 | 180.6 | °C/W |
ΨJT | Junction-to-top characterization parameter | 115.4 | 120.6 | °C/W |
ΨJB | Junction-to-board characterization parameter | 183.4 | 179.5 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | TA = 25°C | -40°C to 125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | ||||
VOH | IOH = -50μA | 1.65V to 5.5V | VCC-0.1 | VCC-0.1 | V | ||||
IOH = -2mA | 1.65V | 1.28 | 1.7(1) | 1.21 | |||||
IOH = -3mA | 2.25V | 2 | 2.4(1) | 1.93 | |||||
IOH = -5.5mA | 3.0V | 2.6 | 3.08(1) | 2.49 | |||||
IOH = -8mA | 4.5V | 4.1 | 4.65(1) | 3.95 | |||||
VOL | IOH = 50μA | 1.65V to 5.5V | 0.1 | 0.1 | V | ||||
IOH = 2mA | 1.65V | 0.1(1) | 0.2 | 0.25 | |||||
IOH = 3mA | 2.25V | 0.1(1) | 0.15 | 0.2 | |||||
IOH = 5.5mA | 3.0V | 0.2(1) | 0.2 | 0.25 | |||||
IOH = 8mA | 4.5V | 0.3(1) | 0.3 | 0.35 | |||||
ICC | VI = VCC or GND, IO = 0 | 5V | 0.12 | ±1 | µA | ||||
3.3V | 1 | 10 | |||||||
2.5V | 1 | 10 | |||||||
1.8V | 1 | 10 | |||||||
ΔICC | One input at 0.3V or 3.4V, other inputs at VCC or GND | 5.5V | 1.35 | 1.5 | mA | ||||
One input at 0.3V or 1.1V, other inputs at VCC or GND | 1.8V | 10 | 10 | µA | |||||
II | VI = 0V to VCC | 0.12 | ±1 | µA | |||||
Ci | VI = VCC or GND | 3.3V | 2 | 10 | 2 | 10 | pF | ||
CO | Vo = VCC or GND | 3.3V | 2.5 | 2.5 | pF | ||||
CPD(2)(3) | F = 1MHz and 10MHz | 5.5V | 14 | pF |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | LOAD CAPACITANCE | TA = 25°C | -40°C to 125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||||
TPD | A | Y | CL = 15pF | 8.8 | 12.7 | 1 | 10.4 | 14.9 | nS | |
CL = 50pF | 10.8 | 15.7 | 1 | 12.7 | 18.3 |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | LOAD CAPACITANCE | TA = 25°C | -40°C to 125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||||
TPD | A | Y | CL = 15pF | 6.3 | 7.9 | 1 | 7.4 | 9.5 | nS | |
CL = 50pF | 7.4 | 9.6 | 1 | 8.9 | 11.5 |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | LOAD CAPACITANCE | TA = 25°C | -40°C to 125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||||
TPD | A | Y | CL = 15pF | 4.9 | 5.9 | 1 | 6 | 7.3 | nS | |
CL = 50pF | 5.9 | 7.2 | 1 | 7.1 | 8.8 |
PARAMETER | FROM (INPUT) | TO (OUTPUT) | LOAD CAPACITANCE | TA = 25°C | -40°C to 125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||||
TPD | A | Y | CL = 15pF | 3.4 | 4.1 | 1 | 4.1 | 4.7 | nS | |
CL = 50pF | 3.9 | 5.3 | 1 | 4.9 | 6.3 |
TA = 25°C (unless otherwise noted)
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
The SN74LV1T04-Q1 contains a single inverter gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the three states that these outputs can be in. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10-kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only as shown in Figure 7-1.
The SN74LV1T04-Q1 belongs to TI's LVxT family of logic devices with integrated voltage level translation. This family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs tolerant of signals with up to 5.5V levels to support down-translation. The output voltage will always be referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. For proper functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or below the specified VIL(MAX) for a LOW input state. Figure 7-2 shows the typical VIH and VIL levels for the LVxT family of devices, as well as the voltage levels for standard CMOS devices for comparison.
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
The inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in the Implications of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ resistor is recommended and will typically meet all requirements.
Signals can be translated down using the SN74LV1T04-Q1. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0V in the LOW state. As shown in Figure 7-2, ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5V, and input signals in the LOW state are lower than VIL(MAX).
As shown in Figure 7-3, for example, the standard CMOS inputs for devices operating at 5.0V, 3.3V or 2.5V can be down-translated to match 1.8V CMOS signals when operating from 1.8V VCC.
Down Translation Combinations are as follows:
Input signals can be up translated using the SN74LV1T04-Q1. The voltage applied at VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0V in the LOW state.
The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5V supply will have a VIH(MIN) of 3.5V. For the SN74LV1T04-Q1, VIH(MIN) with a 5V supply is only 2V, which would allow for up-translation from a typical 2.5V to 5V signals.
As shown in Figure 7-3, ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX).
Up Translation Combinations are as follows:
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
The SN74LV1T04-Q1 can be used to drive signals over relatively long traces or transmission lines. To reduce ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series damping resistor placed in series with the transmitter’s output can be used. The plot in the Application Curve section shows the received signal with three separate resistor values. Just a small amount of resistance can make a significant impact on signal integrity in this type of application.
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74LV1T04-Q1 plus the maximum static supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74LV1T04-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The SN74LV1T04-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50pF.
The SN74LV1T04-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in the CMOS Power Consumption and Cpd Calculation application note.
Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application note.
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74LV1T04-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor value is often used due to these factors.
The SN74LV1T04-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example.
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient.
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.