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SN74LV1T125 Single Power Supply Single Buffer Gate with 3-State Output CMOS Logic Level Shifter
SCLS745D
December 2013 – March 2024
SN74LV1T125
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SN74LV1T125 Single Power Supply Single Buffer Gate with 3-State Output CMOS Logic Level Shifter
1
1
Features
2
Applications
3
Description
4
Related Products
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Operating Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Clamp Diode Structure
8.3.2
Balanced CMOS Push-Pull Outputs
8.3.3
LVxT Enhanced Input Voltage
8.3.3.1
Down Translation
8.3.3.2
Up Translation
8.4
Device Functional Modes
9
Application Information Disclaimer
9.1
Layout
9.1.1
Layout Guidelines
9.2
Power Supply Recommendations
10
Device and Documentation Support
10.1
Documentation Support (Analog)
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DCK|5
MPDS025K
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scls745d_oa
scls745d_pm
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SN74LV1T125 Single Power Supply Single Buffer Gate with 3-State Output CMOS Logic Level Shifter