SN74LV8154 Dual 16-Bit Binary Counters With 3-State Output Registers

1 Features

Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
8-bit counter read bus
2-V to 5.5-V V_CC Operation
Maximum t_pd of 25 ns at 5 V (RCLK to Y)
Typical V_OLP (Output Ground Bounce)
< 0.7 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 4.4 V at V_CC = 5 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)