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  • TLE4275-Q1 5-V Low-Dropout Voltage Regulator

    • SLVS647I August   2006  – November 2014 TLE4275-Q1

      UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TLE4275-Q1 5-V Low-Dropout Voltage Regulator
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulated Output (OUT)
      2. 8.3.2 Power-On-Reset (RESET)
      3. 8.3.3 Reset Delay Timer (DELAY)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Voltage Tracking
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power-Up Reset Capacitance
        2. 9.2.2.2 Thermal Consideration
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTT|5
  • PWP|20
  • KVU|5
Thermal pad, mechanical data (Package|Pins)
  • PWP|20
    • PPTD122Q
  • KVU|5
    • QFND405
  • KTT|5
    • PPTD069B
Orderable Information
  • slvs647i_oa
  • slvs647i_pm
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DATA SHEET

TLE4275-Q1 5-V Low-Dropout Voltage Regulator

1 Features

  • Qualified for Automotive Applications
  • Output Voltage 5 V ± 2%
  • Very Low Current Consumption
  • Power-On and Undervoltage Reset
  • Reset Low-Level Output Voltage < 1 V
  • Very Low Dropout Voltage
  • Short-Circuit Proof
  • Reverse-Polarity Proof

2 Applications

  • Qualified for Automotive Applications
  • Cluster
  • Body Control Modules
  • Heating Ventilation and Air Conditioning (HVAC)

3 Description

The TLE4275-Q1 is a monolithic integrated low-dropout voltage regulator offered in a 5-pin TO package. The device regulates an input voltage up to 45 V to VOUT = 5 V (typical). The device can drive loads up to 450 mA and is short-circuit proof. At overtemperature, the incorporated temperature protection turns off the TLE4275-Q1. The device generates a reset signal for an output voltage, VOUT,rt, of 4.65 V (typical). By the use of an external delay capacitor, one can program the reset delay time.

The input capacitor, CIN, compensates for line fluctuation. Using a resistor of approximately 1 Ω in series with CIN dampens the oscillation of input inductance and input capacitance. The output capacitor, COUT, stabilizes the regulation circuit. The specification for stability is at COUT ≥ 22 μF and ESR ≤ 5 Ω, within the operating temperature range. Stability for electrolytic capacitors specifically is at COUT ≥ 68 µF within the operating temperature range. See the application report on low-temperature stability, SLVA501, for further details.

The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor through a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The device also incorporates a number of internal circuits for protection against: overload, overtemperature, and reverse polarity.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLE4275-Q1 DDPAK/TO-263 (5) 10.16 mm × 8.42 mm
TO-252 (5) 6.10 mm × 6.60 mm
HTSSOP (20) 6.50 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

TLE4275-Q1 data_1_SLVS647.gif

4 Revision History

Changes from H Revision (March 2013) to I Revision

  • Added Applications, Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed KTT values in Thermal Information table Go

Changes from G Revision (January 2013) to H Revision

  • Deleted row for θJA from Absolute Maximum Ratings tableGo

Changes from F Revision (May 2011) to G Revision

  • Updated Pin Functions table with PWP package pin information.Go

5 Pin Configuration and Functions

KTT Package
5-Pin DDPAK/TO-263
Top View
TLE4275-Q1 po_5_ktt_slvs647.gif
KVU Package
5-Pin TO-252
Top View
TLE4275-Q1 po_5_kvu_slvs647.gif
PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
TLE4275-Q1 po_20_htssop_slvs647.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
KTT KVU PWP
DELAY 4 4 3 O Reset delay. Connect to ground with a capacitor to set delay time.
GND 3 3 8 O Ground. Internally connected to heatsink
IN 1 1 19 I Input. Connect to ground as close to device as possible, through a ceramic capacitor.
NC — — 2, 5–7, 9–18, 20 — Not connected
OUT 5 5 4 O Output. Connect to ground with ≥ 22-µF capacitor, ESR < 5 Ω at 10 kHz.
RESET 2 2 1 I Reset output. Open-collector output

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage range(2) IN –42 45 V
DELAY –0.3 7
VO Output voltage range OUT –1 16 V
RESET –0.3 25
II Input current DELAY ±2 mA
IO Output current RESET ±5 mA
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
(3) MM ESD rating tested per JESD22-A115.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) 6000 V
Machine model (MM)(3) 400
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage 5.5 42 V
TJ Junction temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1) TLE4275-Q1 UNIT
KTT KVU PWP
5 PINS 5 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 32.8 40.3 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.0 31.8 22.7
RθJB Junction-to-board thermal resistance 5.3 17.2 19.1
ψJT Junction-to-top characterization parameter 6.3 2.8 0.6
ψJB Junction-to-board characterization parameter 5.4 17.1 18.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 0.7 1.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953) .

6.5 Electrical Characteristics

over recommended operating free-air temperature range, VI = 13.5 V, TJ = −40°C to 150°C (unless otherwise noted) (see Figure 18)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Output voltage IO = 5 mA to 400 mA, VI = 6 V to 28 V 4.9 5 5.1 V
IO = 5 mA to 200 mA, VI = 6 V to 40 V 4.9 5 5.1
IO Output current limit 450 700 950 mA
Iq Current consumption, Iq = II − IO IO = 1 mA TJ = 25°C 150 200 μA
TJ ≤ 85°C 150 220
IO = 250 mA 5 10 mA
IO = 400 mA 12 22
VDO Dropout voltage(1) IO = 300 mA, Vdo = VI − VO 250 500 mV
Load regulation IO = 5 mA to 400 mA 15 30 mV
Line regulation ΔVI = 8 V to 32 V, IO = 5 mA –15 5 15 mV
PSRR Power-supply ripple rejection fr = 100 Hz, Vr = 0.5 Vpp 60 dB
TLE4275-Q1 q_v_drift_lvs647.gif Temperature output-voltage drift 0.5 mV/K
VO,rt RESET switching threshold 4.5 4.65 4.8 V
VROL RESET output low voltage Rext ≥ 5 kΩ, VO > 1 V 0.2 0.4 V
IROH RESET output leakage current VROH = 5 V 0 10 μA
ID,c RESET charging current VD = 1 V 3 5.5 9 μA
VDU RESET upper timing threshold 1.5 1.8 2.2 V
VDRL RESET lower timing threshold 0.2 0.4 0.7 V
(1) Measured when the output voltage VO has dropped 100 mV from the nominal value obtained at VI = 13.5 V

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trd RESET delay time CD = 47 nF 10 16 22 ms
trr RESET reaction time CD = 47 nF 0.5 2 µs
TLE4275-Q1 reset_timing_lvs647.gifFigure 1. Reset Timing Diagram

6.7 Typical Characteristics

At TA = 25ºC
TLE4275-Q1 D011_slvscy0.gif
VI = 6 V
Figure 2. Output Voltage vs Junction Temperature
TLE4275-Q1 D013_slvscy0.gif
Figure 4. Output Voltage vs Input Voltage
TLE4275-Q1 g_iq_io_max35.gif
VI = 13.5 V
Figure 6. Current Consumption vs Output Current
TLE4275-Q1 D009_slvscy0.gif
TJ = 25°C
Figure 8. Dropout Voltage (Vdo) vs Output Current
TLE4275-Q1 D010_slvscy0.gif
VI = 13.5 V
Figure 10. Delay Switching Threshold vs Junction Temperature
TLE4275-Q1 D005_slvscy0.gif
VI = 13.5 V Load = 200 mA COUT = 22 µF
Figure 12. Power-Supply Ripple Rejection vs Frequency
TLE4275-Q1 D007_slvscy0.gif
Figure 14. Thermal Resistance vs Copper Land Pad Area (JEDEC 51-3 Low-K Board)
TLE4275-Q1 g_esr_stability_vs_iload_v2_lvs647.gif
Figure 16. ESR Stability vs Load Current
TLE4275-Q1 D012_slvscy0.gif
VI = 28 V
Figure 3. Output Voltage vs Junction Temperature
TLE4275-Q1 D002_slvscy0.gif
Figure 5. Output Current vs Junction Temperature
TLE4275-Q1 D003_slvscy0.gif
VI = 13.5 V
Figure 7. Current Consumption vs Output Current
TLE4275-Q1 D001_slvscy0.gif
VI = 13.5 V VD = 1 V
Figure 9. Charge Current (ID,C) vs Junction Temperature
TLE4275-Q1 D004_slvscy0.gif
VI = 13.5 V Load = 1 mA COUT = 22 µF
Figure 11. Power-Supply Ripple Rejection vs Frequency
TLE4275-Q1 D006_slvscy0.gif
VI = 13.5 V Load = 400 mA COUT = 22 µF
Figure 13. Power-Supply Ripple Rejection vs Frequency
TLE4275-Q1 D008_slvscy0.gif
Figure 15. Thermal Resistance vs Pulse Width Time for Various Duty Cycles
TLE4275-Q1 g_esr_stability_vs_cload_v2_lvs647.gif
Figure 17. ESR Stability vs Load Capacitance

 
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