SLAS715C
June 2010 – January 2023
TLV320AIC3104-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Switching Characteristics I2S/LJF/RJF Timing in Master Mode
8.7
Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
8.8
Switching Characteristics DSP Timing in Master Mode
8.9
Switching Characteristics DSP Timing in Slave Mode
8.10
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Audio Data Converters
9.3.2
Stereo Audio ADC
9.3.2.1
Stereo Audio ADC High-Pass Filter
9.3.3
Automatic Gain Control (AGC)
9.3.4
Stereo Audio DAC
9.3.5
Digital Audio Processing for Playback
9.3.6
Digital Interpolation Filter
9.3.7
Delta-Sigma Audio DAC
9.3.8
Audio DAC Digital Volume Control
9.3.9
Analog Output Common-mode Adjustment
9.3.10
Audio DAC Power Control
9.3.11
Audio Analog Inputs
9.3.12
Analog Input Bypass Path Functionality
9.3.13
ADC PGA Signal Bypass Path Functionality
9.3.14
Input Impedance and VCM Control
9.3.15
MICBIAS Generation
9.3.16
Analog Fully Differential Line Output Drivers
9.3.17
Analog High-Power Output Drivers
9.3.18
Short-Circuit Output Protection
9.3.19
Jack and Headset Detection
9.4
Device Functional Modes
9.4.1
Digital Audio Processing for Record Path
9.4.2
Increasing DAC Dynamic Range
9.4.3
Passive Analog Bypass During Power Down
9.4.4
Hardware Reset
9.5
Programming
9.5.1
Digital Control Serial Interface
9.5.2
I2C Control Interface
9.5.3
I2C Bus Debug in a Glitched System
9.5.4
Digital Audio Data Serial Interface
9.5.5
Right-Justified Mode
9.5.6
Left-Justified Mode
9.5.7
I2S Mode
9.5.8
DSP Mode
9.5.9
TDM Data Transfer
9.5.10
Audio Clock Generation
9.6
Register Maps
9.6.1
Output Stage Volume Controls
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
External Speaker Driver in Infotainment and Cluster Applications
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
External Speaker Amplifier With Separate Line Outputs
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Device Nomenclature
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Community Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND029X
Orderable Information
slas715c_oa
slas715c_pm
1
Features
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
Device Temperature Grade 3: –40°C to 105°C
Ambient Operating Temperature Range
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C6
Stereo Audio DAC:
102-dBA Signal-to-Noise Ratio
16-, 20-, 24-, or 32-Bit Data
Supports Sample Rates From 8 kHz to 96 kHz
3D, Bass, Treble, EQ, De-Emphasis Effects
Flexible Power Saving Modes and
Performance are Available
Stereo Audio ADC:
92-dBA Signal-to-Noise Ratio
Supports Sample Rates From 8 kHz to 96 kHz
Digital Signal Processing and Noise Filtering
available during record
Six Audio Input Pins:
One Stereo Pair of Single-Ended Inputs
One Stereo Pair of Fully Differential Inputs
Six Audio Output Drivers:
Fully Differential or Single-Ended Stereo Headphone Drivers
Fully Differential Stereo Line Outputs
Low Power: 14-mW Stereo, 48-kHz Playback With 3.3-V Analog Supply
Ultralow-Power Mode With Passive Analog Bypass
Programmable Input/Output Analog Gains
Automatic Gain Control (AGC) for Record
Programmable Microphone Bias Level
Programmable PLL for Flexible Clock Generation
I
2
C Control Bus
Audio Serial Data Bus Supports I
2
S, Left/RightJustified, DSP, and TDM Modes
Extensive Modular Power Control
Power Supplies:
Analog: 2.7 V to 3.6 V
Digital Core: 1.525 V to 1.95 V
Digital I/O: 1.1 V to 3.6 V